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[RISCV] Remove x7 from fastcc list. #96729

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Merged
merged 3 commits into from
Jul 17, 2024
Merged

[RISCV] Remove x7 from fastcc list. #96729

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2221e45
[RISCV] Remove x7 from fastcc list.
Jun 26, 2024
09acc16
Add comments about the reason to remove x7.
Jul 16, 2024
440a556
fix code format.
Jul 16, 2024
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9 changes: 4 additions & 5 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -18884,15 +18884,14 @@ ArrayRef<MCPhysReg> RISCV::getArgGPRs(const RISCVABI::ABI ABI) {
static ArrayRef<MCPhysReg> getFastCCArgGPRs(const RISCVABI::ABI ABI) {
// The GPRs used for passing arguments in the FastCC, X5 and X6 might be used
// for save-restore libcall, so we don't use them.
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Please update the comment to indicate why we don't use X7.

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Updated.

// Don't use X7 for fastcc, since Zicfilp uses X7 as the label register.
static const MCPhysReg FastCCIGPRs[] = {
RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14,
RISCV::X15, RISCV::X16, RISCV::X17, RISCV::X7, RISCV::X28,
RISCV::X29, RISCV::X30, RISCV::X31};
RISCV::X10, RISCV::X11, RISCV::X12, RISCV::X13, RISCV::X14, RISCV::X15,
RISCV::X16, RISCV::X17, RISCV::X28, RISCV::X29, RISCV::X30, RISCV::X31};

// The GPRs used for passing arguments in the FastCC when using ILP32E/ILP64E.
static const MCPhysReg FastCCEGPRs[] = {RISCV::X10, RISCV::X11, RISCV::X12,
RISCV::X13, RISCV::X14, RISCV::X15,
RISCV::X7};
RISCV::X13, RISCV::X14, RISCV::X15};

if (ABI == RISCVABI::ABI_ILP32E || ABI == RISCVABI::ABI_LP64E)
return ArrayRef(FastCCEGPRs);
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34 changes: 18 additions & 16 deletions llvm/test/CodeGen/RISCV/fastcc-int.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -32,16 +32,17 @@ define i32 @caller(<16 x i32> %A) nounwind {
; RV32-NEXT: lw a5, 20(a0)
; RV32-NEXT: lw a6, 24(a0)
; RV32-NEXT: lw a7, 28(a0)
; RV32-NEXT: lw t2, 32(a0)
; RV32-NEXT: lw t3, 36(a0)
; RV32-NEXT: lw t4, 40(a0)
; RV32-NEXT: lw t5, 44(a0)
; RV32-NEXT: lw t6, 48(a0)
; RV32-NEXT: lw t1, 52(a0)
; RV32-NEXT: lw t3, 32(a0)
; RV32-NEXT: lw t4, 36(a0)
; RV32-NEXT: lw t5, 40(a0)
; RV32-NEXT: lw t6, 44(a0)
; RV32-NEXT: lw t1, 48(a0)
; RV32-NEXT: lw t2, 52(a0)
; RV32-NEXT: lw s0, 56(a0)
; RV32-NEXT: lw a0, 60(a0)
; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: sw s0, 4(sp)
; RV32-NEXT: sw a0, 12(sp)
; RV32-NEXT: sw s0, 8(sp)
; RV32-NEXT: sw t2, 4(sp)
; RV32-NEXT: sw t1, 0(sp)
; RV32-NEXT: mv a0, t0
; RV32-NEXT: call callee
Expand All @@ -63,16 +64,17 @@ define i32 @caller(<16 x i32> %A) nounwind {
; RV64-NEXT: ld a5, 40(a0)
; RV64-NEXT: ld a6, 48(a0)
; RV64-NEXT: ld a7, 56(a0)
; RV64-NEXT: ld t2, 64(a0)
; RV64-NEXT: ld t3, 72(a0)
; RV64-NEXT: ld t4, 80(a0)
; RV64-NEXT: ld t5, 88(a0)
; RV64-NEXT: ld t6, 96(a0)
; RV64-NEXT: ld t1, 104(a0)
; RV64-NEXT: ld t3, 64(a0)
; RV64-NEXT: ld t4, 72(a0)
; RV64-NEXT: ld t5, 80(a0)
; RV64-NEXT: ld t6, 88(a0)
; RV64-NEXT: ld t1, 96(a0)
; RV64-NEXT: ld t2, 104(a0)
; RV64-NEXT: ld s0, 112(a0)
; RV64-NEXT: ld a0, 120(a0)
; RV64-NEXT: sd a0, 16(sp)
; RV64-NEXT: sd s0, 8(sp)
; RV64-NEXT: sd a0, 24(sp)
; RV64-NEXT: sd s0, 16(sp)
; RV64-NEXT: sd t2, 8(sp)
; RV64-NEXT: sd t1, 0(sp)
; RV64-NEXT: mv a0, t0
; RV64-NEXT: call callee
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