[MLIR][OpenMP] Lowering support for Order clause in SIMD directive #96866
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@llvm/pr-subscribers-mlir @llvm/pr-subscribers-flang-openmp Author: None (harishch4) ChangesFull diff: https://github.com/llvm/llvm-project/pull/96866.diff 2 Files Affected:
diff --git a/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp b/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
index eabc4b30f57a9..5b9457f860479 100644
--- a/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
+++ b/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
@@ -1543,7 +1543,9 @@ convertOmpSimd(Operation &opInst, llvm::IRBuilderBase &builder,
loopInfo, alignedVars,
simdOp.getIfExpr() ? moduleTranslation.lookupValue(simdOp.getIfExpr())
: nullptr,
- llvm::omp::OrderKind::OMP_ORDER_unknown, simdlen, safelen);
+ simdOp.getOrderVal() ? llvm::omp::OrderKind::OMP_ORDER_concurrent
+ : llvm::omp::OrderKind::OMP_ORDER_unknown,
+ simdlen, safelen);
builder.restoreIP(afterIP);
return success();
diff --git a/mlir/test/Target/LLVMIR/openmp-llvm.mlir b/mlir/test/Target/LLVMIR/openmp-llvm.mlir
index a1cc76f9ab770..5b68a25f218c3 100644
--- a/mlir/test/Target/LLVMIR/openmp-llvm.mlir
+++ b/mlir/test/Target/LLVMIR/openmp-llvm.mlir
@@ -826,6 +826,30 @@ llvm.func @simd_if(%arg0: !llvm.ptr {fir.bindc_name = "n"}, %arg1: !llvm.ptr {fi
// -----
+// CHECK-LABEL: @simd_order
+llvm.func @simd_order() {
+ %0 = llvm.mlir.constant(1 : i64) : i64
+ %1 = llvm.alloca %0 x i32 {bindc_name = "i", pinned} : (i64) -> !llvm.ptr
+ %2 = llvm.mlir.constant(1 : i64) : i64
+ %3 = llvm.alloca %2 x i32 {bindc_name = "i"} : (i64) -> !llvm.ptr
+ %4 = llvm.mlir.constant(1 : i32) : i32
+ %5 = llvm.mlir.constant(10 : i32) : i32
+ %6 = llvm.mlir.constant(1 : i32) : i32
+ omp.simd order(concurrent) safelen(2) {
+ omp.loop_nest (%arg0) : i32 = (%4) to (%5) inclusive step (%6) {
+ llvm.store %arg0, %1 : i32, !llvm.ptr
+ omp.yield
+ }
+ }
+ llvm.return
+}
+// If clause order(concurrent) is specified then the memory instructions
+// are marked parallel even if 'safelen' is finite.
+// CHECK: llvm.loop.parallel_accesses
+// CHECK-NEXT: llvm.loop.vectorize.enable
+// CHECK-NEXT: llvm.loop.vectorize.width{{.*}}i64 2
+// -----
+
llvm.func @body(i64)
llvm.func @test_omp_wsloop_ordered(%lb : i64, %ub : i64, %step : i64) -> () {
|
skatrak
reviewed
Jun 27, 2024
Comment on lines
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| simdOp.getOrderVal() ? llvm::omp::OrderKind::OMP_ORDER_concurrent | ||
| : llvm::omp::OrderKind::OMP_ORDER_unknown, |
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Isn't it technically possible to do omp.simd order(unknown) { ... }? Maybe you can add a test for that and potentially modify this to make sure it works too.
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Present implementation doesn't allow anything other than concurrent, example.
Comment on lines
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| llvm.func @simd_order() { | ||
| %0 = llvm.mlir.constant(1 : i64) : i64 | ||
| %1 = llvm.alloca %0 x i32 {bindc_name = "i", pinned} : (i64) -> !llvm.ptr | ||
| %2 = llvm.mlir.constant(1 : i64) : i64 | ||
| %3 = llvm.alloca %2 x i32 {bindc_name = "i"} : (i64) -> !llvm.ptr | ||
| %4 = llvm.mlir.constant(1 : i32) : i32 | ||
| %5 = llvm.mlir.constant(10 : i32) : i32 | ||
| %6 = llvm.mlir.constant(1 : i32) : i32 | ||
| omp.simd order(concurrent) safelen(2) { | ||
| omp.loop_nest (%arg0) : i32 = (%4) to (%5) inclusive step (%6) { | ||
| llvm.store %arg0, %1 : i32, !llvm.ptr | ||
| omp.yield | ||
| } | ||
| } | ||
| llvm.return | ||
| } |
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You could simplify the test to something like.
llvm.func @simd_order() {
%0 = llvm.mlir.constant(10 : i64) : i64
%1 = llvm.mlir.constant(1 : i64) : i64
%2 = llvm.alloca %1 x i64 : (i64) -> !llvm.ptr
omp.simd order(concurrent) safelen(2) {
omp.loop_nest (%arg0) : i64 = (%1) to (%0) inclusive step (%1) {
llvm.store %arg0, %2 : i64, !llvm.ptr
omp.yield
}
}
llvm.return
}
Comment on lines
1546
to
1547
| simdOp.getOrderVal() ? llvm::omp::OrderKind::OMP_ORDER_concurrent | ||
| : llvm::omp::OrderKind::OMP_ORDER_unknown, |
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I see that OrderVal is an enum (not a unit attribute) but only with a single value. Would it be better to have a switch so that any future updates will hit an error and not silently pass concurrent?
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Okay, make sense.
| } | ||
| // If clause order(concurrent) is specified then the memory instructions | ||
| // are marked parallel even if 'safelen' is finite. | ||
| // CHECK: llvm.loop.parallel_accesses |
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Is it the parallel accesses that comes with concurrent?
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Yes, simliar to what clang is doing in CodeGenFunction::EmitOMPSimdInit().
skatrak
approved these changes
Jun 27, 2024
lravenclaw
pushed a commit
to lravenclaw/llvm-project
that referenced
this pull request
Jul 3, 2024
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