[RISCV] Update SiFive VCIX documentation link. NFC #96986
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The previous version of the document did not prefix the intrinsic names with __riscv_. That has been corrected now. We have always implemented the intrinsics with the __riscv_ prefix so now the documentation matches our implementation. The document is now labeled as 1.1, but I have not changed the extension version in the compiler since it was only changing the intrinsic names.
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@llvm/pr-subscribers-backend-risc-v Author: Craig Topper (topperc) ChangesThe previous version of the document did not prefix the intrinsic names with _riscv. That has been corrected now. We have always implemented the intrinsics with the _riscv prefix so now the documentation matches our implementation. The document is now labeled as 1.1, but I have not changed the extension version in the compiler since it was only changing the intrinsic names. Full diff: https://github.com/llvm/llvm-project/pull/96986.diff 1 Files Affected:
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 5f3e7e6bd1131..f6a3712bbc298 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -330,7 +330,7 @@ The current vendor extensions supported are:
LLVM implements `version 1.0.0 of the VTx-family custom instructions specification <https://github.com/ventanamicro/ventana-custom-extensions/releases/download/v1.0.0/ventana-custom-extensions-v1.0.0.pdf>`__ by Ventana Micro Systems. All instructions are prefixed with `vt.` as described in the specification, and the riscv-toolchain-convention document linked above. These instructions are only available for riscv64 at this time.
``XSfvcp``
- LLVM implements `version 1.0.0 of the SiFive Vector Coprocessor Interface (VCIX) Software Specification <https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf>`__ by SiFive. All instructions are prefixed with `sf.vc.` as described in the specification, and the riscv-toolchain-convention document linked above.
+ LLVM implements `version 1.1.0 of the SiFive Vector Coprocessor Interface (VCIX) Software Specification <https://sifive.cdn.prismic.io/sifive/Zn3m1R5LeNNTwnLS_vcix-spec-software-v1p1.pdf>`__ by SiFive. All instructions are prefixed with `sf.vc.` as described in the specification, and the riscv-toolchain-convention document linked above.
``XSfvqmaccdod``, ``XSfvqmaccqoq``
LLVM implements `version 1.1.0 of the SiFive Int8 Matrix Multiplication Extensions Specification <https://sifive.cdn.prismic.io/sifive/1a2ad85b-d818-49f7-ba83-f51f1731edbe_int8-matmul-spec.pdf>`__ by SiFive. All instructions are prefixed with `sf.` as described in the specification linked above.
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wangpc-pp
approved these changes
Jun 28, 2024
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Jul 3, 2024
The previous version of the document did not prefix the intrinsic names with `__riscv_`. That has been corrected now. We have always implemented the intrinsics with the `__riscv_` prefix so now the documentation matches our implementation. The document is now labeled as 1.1, but I have not changed the extension version in the compiler since it was only changing the intrinsic names.
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The previous version of the document did not prefix the intrinsic names with
__riscv_. That has been corrected now. We have always implemented the intrinsics with the__riscv_prefix so now the documentation matches our implementation.The document is now labeled as 1.1, but I have not changed the extension version in the compiler since it was only changing the intrinsic names.