[clang][CodeGen][AMDGPU] Enable AMDGPU printf for spirv64-amd-amdhsa
#97132
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AlexVlx
added
backend:AMDGPU
clang:codegen
|
@llvm/pr-subscribers-backend-amdgpu @llvm/pr-subscribers-clang-codegen Author: Alex Voicu (AlexVlx) ChangesThis enables the AMDGPU specific implementation of Patch is 24.18 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/97132.diff 5 Files Affected:
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 98c2f70664ec7..7a57e53cce09c 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -5888,12 +5888,15 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID,
case Builtin::BI__builtin_printf:
case Builtin::BIprintf:
if (getTarget().getTriple().isNVPTX() ||
- getTarget().getTriple().isAMDGCN()) {
+ getTarget().getTriple().isAMDGCN() ||
+ (getTarget().getTriple().isSPIRV() &&
+ getTarget().getTriple().getVendor() == Triple::VendorType::AMD)) {
if (getLangOpts().OpenMPIsTargetDevice)
return EmitOpenMPDevicePrintfCallExpr(E);
if (getTarget().getTriple().isNVPTX())
return EmitNVPTXDevicePrintfCallExpr(E);
- if (getTarget().getTriple().isAMDGCN() && getLangOpts().HIP)
+ if ((getTarget().getTriple().isAMDGCN() ||
+ getTarget().getTriple().isSPIRV()) && getLangOpts().HIP)
return EmitAMDGPUDevicePrintfCallExpr(E);
}
diff --git a/clang/lib/CodeGen/CGGPUBuiltin.cpp b/clang/lib/CodeGen/CGGPUBuiltin.cpp
index bd95541647bcf..b2340732afeb5 100644
--- a/clang/lib/CodeGen/CGGPUBuiltin.cpp
+++ b/clang/lib/CodeGen/CGGPUBuiltin.cpp
@@ -179,7 +179,9 @@ RValue CodeGenFunction::EmitNVPTXDevicePrintfCallExpr(const CallExpr *E) {
}
RValue CodeGenFunction::EmitAMDGPUDevicePrintfCallExpr(const CallExpr *E) {
- assert(getTarget().getTriple().getArch() == llvm::Triple::amdgcn);
+ assert(getTarget().getTriple().isAMDGCN() ||
+ (getTarget().getTriple().isSPIRV() &&
+ getTarget().getTriple().getVendor() == llvm::Triple::AMD));
assert(E->getBuiltinCallee() == Builtin::BIprintf ||
E->getBuiltinCallee() == Builtin::BI__builtin_printf);
assert(E->getNumArgs() >= 1); // printf always has at least one arg.
diff --git a/clang/test/CodeGenHIP/printf-builtin.hip b/clang/test/CodeGenHIP/printf-builtin.hip
index df1fbbb6d637a..506bb6a175872 100644
--- a/clang/test/CodeGenHIP/printf-builtin.hip
+++ b/clang/test/CodeGenHIP/printf-builtin.hip
@@ -1,8 +1,12 @@
// REQUIRES: amdgpu-registered-target
// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -emit-llvm -disable-llvm-optzns -mprintf-kind=hostcall -fno-builtin-printf -fcuda-is-device \
// RUN: -o - %s | FileCheck --check-prefixes=CHECK,HOSTCALL %s
+// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -emit-llvm -disable-llvm-optzns -mprintf-kind=hostcall -fno-builtin-printf -fcuda-is-device \
+// RUN: -o - %s | FileCheck --check-prefixes=CHECK-AMDGCNSPIRV,HOSTCALL-AMDGCNSPIRV %s
// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -emit-llvm -disable-llvm-optzns -mprintf-kind=buffered -fno-builtin-printf -fcuda-is-device \
// RUN: -o - %s | FileCheck --check-prefixes=CHECK,BUFFERED %s
+// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -emit-llvm -disable-llvm-optzns -mprintf-kind=buffered -fno-builtin-printf -fcuda-is-device \
+// RUN: -o - %s | FileCheck --check-prefixes=CHECK-AMDGCNSPIRV,BUFFERED-AMDGCNSPIRV %s
#define __device__ __attribute__((device))
@@ -11,13 +15,17 @@ extern "C" __device__ int printf(const char *format, ...);
// CHECK-LABEL: @_Z4foo1v()
__device__ int foo1() {
// HOSTCALL: call i64 @__ockl_printf_begin
+ // HOSTCALL-AMDGCNSPIRV: call addrspace(4) i64 @__ockl_printf_begin
// BUFFERED: call ptr addrspace(1) @__printf_alloc
+ // BUFFERED-AMDGCNSPIRV: call addrspace(4) ptr addrspace(1) @__printf_alloc
// CHECK-NOT: call i32 (ptr, ...) @printf
+ // CHECK-AMDGCNSPIRV-NOT: call i32 (ptr, ...) @printf
return __builtin_printf("Hello World\n");
}
// CHECK-LABEL: @_Z4foo2v()
__device__ int foo2() {
// CHECK: call i32 (ptr, ...) @printf
+ // CHECK-AMDGCNSPIRV: call spir_func addrspace(4) i32 (ptr addrspace(4), ...) @printf
return printf("Hello World\n");
}
diff --git a/clang/test/CodeGenHIP/printf.cpp b/clang/test/CodeGenHIP/printf.cpp
index 8c8b801dbbf56..2d814d6fdc704 100644
--- a/clang/test/CodeGenHIP/printf.cpp
+++ b/clang/test/CodeGenHIP/printf.cpp
@@ -1,44 +1,219 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
// REQUIRES: amdgpu-registered-target
// RUN: %clang_cc1 -triple amdgcn-amd-amdhsa -x hip -emit-llvm -fcuda-is-device \
-// RUN: -o - %s | FileCheck --enable-var-scope %s
+// RUN: -o - %s | FileCheck --check-prefix=AMDGCN --enable-var-scope %s
+// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -x hip -emit-llvm -fcuda-is-device \
+// RUN: -o - %s | FileCheck --check-prefix=AMDGCNSPIRV --enable-var-scope %s
#define __device__ __attribute__((device))
extern "C" __device__ int printf(const char *format, ...);
+// AMDGCN-LABEL: define dso_local noundef i32 @_Z4foo1v(
+// AMDGCN-SAME: ) #[[ATTR0:[0-9]+]] {
+// AMDGCN-NEXT: [[ENTRY:.*]]:
+// AMDGCN-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5)
+// AMDGCN-NEXT: [[S:%.*]] = alloca ptr, align 8, addrspace(5)
+// AMDGCN-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr
+// AMDGCN-NEXT: [[S_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[S]] to ptr
+// AMDGCN-NEXT: store ptr addrspacecast (ptr addrspace(4) @.str to ptr), ptr [[S_ASCAST]], align 8
+// AMDGCN-NEXT: [[TMP0:%.*]] = load ptr, ptr [[S_ASCAST]], align 8
+// AMDGCN-NEXT: [[TMP1:%.*]] = load ptr, ptr [[S_ASCAST]], align 8
+// AMDGCN-NEXT: [[TMP2:%.*]] = call i64 @__ockl_printf_begin(i64 0)
+// AMDGCN-NEXT: [[TMP3:%.*]] = icmp eq ptr addrspacecast (ptr addrspace(4) @.str.1 to ptr), null
+// AMDGCN-NEXT: br i1 [[TMP3]], label %[[STRLEN_JOIN:.*]], label %[[STRLEN_WHILE:.*]]
+// AMDGCN: [[STRLEN_WHILE]]:
+// AMDGCN-NEXT: [[TMP4:%.*]] = phi ptr [ addrspacecast (ptr addrspace(4) @.str.1 to ptr), %[[ENTRY]] ], [ [[TMP5:%.*]], %[[STRLEN_WHILE]] ]
+// AMDGCN-NEXT: [[TMP5]] = getelementptr i8, ptr [[TMP4]], i64 1
+// AMDGCN-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP4]], align 1
+// AMDGCN-NEXT: [[TMP7:%.*]] = icmp eq i8 [[TMP6]], 0
+// AMDGCN-NEXT: br i1 [[TMP7]], label %[[STRLEN_WHILE_DONE:.*]], label %[[STRLEN_WHILE]]
+// AMDGCN: [[STRLEN_WHILE_DONE]]:
+// AMDGCN-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP4]] to i64
+// AMDGCN-NEXT: [[TMP9:%.*]] = sub i64 [[TMP8]], ptrtoint (ptr addrspacecast (ptr addrspace(4) @.str.1 to ptr) to i64)
+// AMDGCN-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], 1
+// AMDGCN-NEXT: br label %[[STRLEN_JOIN]]
+// AMDGCN: [[STRLEN_JOIN]]:
+// AMDGCN-NEXT: [[TMP11:%.*]] = phi i64 [ [[TMP10]], %[[STRLEN_WHILE_DONE]] ], [ 0, %[[ENTRY]] ]
+// AMDGCN-NEXT: [[TMP12:%.*]] = call i64 @__ockl_printf_append_string_n(i64 [[TMP2]], ptr addrspacecast (ptr addrspace(4) @.str.1 to ptr), i64 [[TMP11]], i32 0)
+// AMDGCN-NEXT: [[TMP13:%.*]] = call i64 @__ockl_printf_append_args(i64 [[TMP12]], i32 1, i64 8, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i32 0)
+// AMDGCN-NEXT: [[TMP14:%.*]] = call i64 @__ockl_printf_append_args(i64 [[TMP13]], i32 1, i64 4614256650576692846, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i32 0)
+// AMDGCN-NEXT: [[TMP15:%.*]] = call i64 @__ockl_printf_append_args(i64 [[TMP14]], i32 1, i64 8, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i32 0)
+// AMDGCN-NEXT: [[TMP16:%.*]] = call i64 @__ockl_printf_append_args(i64 [[TMP15]], i32 1, i64 4, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i32 0)
+// AMDGCN-NEXT: [[TMP17:%.*]] = icmp eq ptr [[TMP0]], null
+// AMDGCN-NEXT: br i1 [[TMP17]], label %[[STRLEN_JOIN1:.*]], label %[[STRLEN_WHILE2:.*]]
+// AMDGCN: [[STRLEN_WHILE2]]:
+// AMDGCN-NEXT: [[TMP18:%.*]] = phi ptr [ [[TMP0]], %[[STRLEN_JOIN]] ], [ [[TMP19:%.*]], %[[STRLEN_WHILE2]] ]
+// AMDGCN-NEXT: [[TMP19]] = getelementptr i8, ptr [[TMP18]], i64 1
+// AMDGCN-NEXT: [[TMP20:%.*]] = load i8, ptr [[TMP18]], align 1
+// AMDGCN-NEXT: [[TMP21:%.*]] = icmp eq i8 [[TMP20]], 0
+// AMDGCN-NEXT: br i1 [[TMP21]], label %[[STRLEN_WHILE_DONE3:.*]], label %[[STRLEN_WHILE2]]
+// AMDGCN: [[STRLEN_WHILE_DONE3]]:
+// AMDGCN-NEXT: [[TMP22:%.*]] = ptrtoint ptr [[TMP0]] to i64
+// AMDGCN-NEXT: [[TMP23:%.*]] = ptrtoint ptr [[TMP18]] to i64
+// AMDGCN-NEXT: [[TMP24:%.*]] = sub i64 [[TMP23]], [[TMP22]]
+// AMDGCN-NEXT: [[TMP25:%.*]] = add i64 [[TMP24]], 1
+// AMDGCN-NEXT: br label %[[STRLEN_JOIN1]]
+// AMDGCN: [[STRLEN_JOIN1]]:
+// AMDGCN-NEXT: [[TMP26:%.*]] = phi i64 [ [[TMP25]], %[[STRLEN_WHILE_DONE3]] ], [ 0, %[[STRLEN_JOIN]] ]
+// AMDGCN-NEXT: [[TMP27:%.*]] = call i64 @__ockl_printf_append_string_n(i64 [[TMP16]], ptr [[TMP0]], i64 [[TMP26]], i32 0)
+// AMDGCN-NEXT: [[TMP28:%.*]] = ptrtoint ptr [[TMP1]] to i64
+// AMDGCN-NEXT: [[TMP29:%.*]] = call i64 @__ockl_printf_append_args(i64 [[TMP27]], i32 1, i64 [[TMP28]], i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i32 1)
+// AMDGCN-NEXT: [[TMP30:%.*]] = trunc i64 [[TMP29]] to i32
+// AMDGCN-NEXT: ret i32 [[TMP30]]
+//
+// AMDGCNSPIRV-LABEL: define spir_func noundef i32 @_Z4foo1v(
+// AMDGCNSPIRV-SAME: ) addrspace(4) #[[ATTR0:[0-9]+]] {
+// AMDGCNSPIRV-NEXT: [[ENTRY:.*]]:
+// AMDGCNSPIRV-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
+// AMDGCNSPIRV-NEXT: [[S:%.*]] = alloca ptr addrspace(4), align 8
+// AMDGCNSPIRV-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr [[RETVAL]] to ptr addrspace(4)
+// AMDGCNSPIRV-NEXT: [[S_ASCAST:%.*]] = addrspacecast ptr [[S]] to ptr addrspace(4)
+// AMDGCNSPIRV-NEXT: store ptr addrspace(4) addrspacecast (ptr addrspace(1) @.str to ptr addrspace(4)), ptr addrspace(4) [[S_ASCAST]], align 8
+// AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[S_ASCAST]], align 8
+// AMDGCNSPIRV-NEXT: [[TMP1:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[S_ASCAST]], align 8
+// AMDGCNSPIRV-NEXT: [[TMP2:%.*]] = call addrspace(4) i64 @__ockl_printf_begin(i64 0)
+// AMDGCNSPIRV-NEXT: [[TMP3:%.*]] = icmp eq ptr addrspace(4) addrspacecast (ptr addrspace(1) @.str.1 to ptr addrspace(4)), null
+// AMDGCNSPIRV-NEXT: br i1 [[TMP3]], label %[[STRLEN_JOIN:.*]], label %[[STRLEN_WHILE:.*]]
+// AMDGCNSPIRV: [[STRLEN_WHILE]]:
+// AMDGCNSPIRV-NEXT: [[TMP4:%.*]] = phi ptr addrspace(4) [ addrspacecast (ptr addrspace(1) @.str.1 to ptr addrspace(4)), %[[ENTRY]] ], [ [[TMP5:%.*]], %[[STRLEN_WHILE]] ]
+// AMDGCNSPIRV-NEXT: [[TMP5]] = getelementptr i8, ptr addrspace(4) [[TMP4]], i64 1
+// AMDGCNSPIRV-NEXT: [[TMP6:%.*]] = load i8, ptr addrspace(4) [[TMP4]], align 1
+// AMDGCNSPIRV-NEXT: [[TMP7:%.*]] = icmp eq i8 [[TMP6]], 0
+// AMDGCNSPIRV-NEXT: br i1 [[TMP7]], label %[[STRLEN_WHILE_DONE:.*]], label %[[STRLEN_WHILE]]
+// AMDGCNSPIRV: [[STRLEN_WHILE_DONE]]:
+// AMDGCNSPIRV-NEXT: [[TMP8:%.*]] = ptrtoint ptr addrspace(4) [[TMP4]] to i64
+// AMDGCNSPIRV-NEXT: [[TMP9:%.*]] = sub i64 [[TMP8]], ptrtoint (ptr addrspace(4) addrspacecast (ptr addrspace(1) @.str.1 to ptr addrspace(4)) to i64)
+// AMDGCNSPIRV-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], 1
+// AMDGCNSPIRV-NEXT: br label %[[STRLEN_JOIN]]
+// AMDGCNSPIRV: [[STRLEN_JOIN]]:
+// AMDGCNSPIRV-NEXT: [[TMP11:%.*]] = phi i64 [ [[TMP10]], %[[STRLEN_WHILE_DONE]] ], [ 0, %[[ENTRY]] ]
+// AMDGCNSPIRV-NEXT: [[TMP12:%.*]] = call addrspace(4) i64 @__ockl_printf_append_string_n(i64 [[TMP2]], ptr addrspace(4) addrspacecast (ptr addrspace(1) @.str.1 to ptr addrspace(4)), i64 [[TMP11]], i32 0)
+// AMDGCNSPIRV-NEXT: [[TMP13:%.*]] = call addrspace(4) i64 @__ockl_printf_append_args(i64 [[TMP12]], i32 1, i64 8, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i32 0)
+// AMDGCNSPIRV-NEXT: [[TMP14:%.*]] = call addrspace(4) i64 @__ockl_printf_append_args(i64 [[TMP13]], i32 1, i64 4614256650576692846, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i32 0)
+// AMDGCNSPIRV-NEXT: [[TMP15:%.*]] = call addrspace(4) i64 @__ockl_printf_append_args(i64 [[TMP14]], i32 1, i64 8, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i32 0)
+// AMDGCNSPIRV-NEXT: [[TMP16:%.*]] = call addrspace(4) i64 @__ockl_printf_append_args(i64 [[TMP15]], i32 1, i64 4, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i32 0)
+// AMDGCNSPIRV-NEXT: [[TMP17:%.*]] = icmp eq ptr addrspace(4) [[TMP0]], null
+// AMDGCNSPIRV-NEXT: br i1 [[TMP17]], label %[[STRLEN_JOIN1:.*]], label %[[STRLEN_WHILE2:.*]]
+// AMDGCNSPIRV: [[STRLEN_WHILE2]]:
+// AMDGCNSPIRV-NEXT: [[TMP18:%.*]] = phi ptr addrspace(4) [ [[TMP0]], %[[STRLEN_JOIN]] ], [ [[TMP19:%.*]], %[[STRLEN_WHILE2]] ]
+// AMDGCNSPIRV-NEXT: [[TMP19]] = getelementptr i8, ptr addrspace(4) [[TMP18]], i64 1
+// AMDGCNSPIRV-NEXT: [[TMP20:%.*]] = load i8, ptr addrspace(4) [[TMP18]], align 1
+// AMDGCNSPIRV-NEXT: [[TMP21:%.*]] = icmp eq i8 [[TMP20]], 0
+// AMDGCNSPIRV-NEXT: br i1 [[TMP21]], label %[[STRLEN_WHILE_DONE3:.*]], label %[[STRLEN_WHILE2]]
+// AMDGCNSPIRV: [[STRLEN_WHILE_DONE3]]:
+// AMDGCNSPIRV-NEXT: [[TMP22:%.*]] = ptrtoint ptr addrspace(4) [[TMP0]] to i64
+// AMDGCNSPIRV-NEXT: [[TMP23:%.*]] = ptrtoint ptr addrspace(4) [[TMP18]] to i64
+// AMDGCNSPIRV-NEXT: [[TMP24:%.*]] = sub i64 [[TMP23]], [[TMP22]]
+// AMDGCNSPIRV-NEXT: [[TMP25:%.*]] = add i64 [[TMP24]], 1
+// AMDGCNSPIRV-NEXT: br label %[[STRLEN_JOIN1]]
+// AMDGCNSPIRV: [[STRLEN_JOIN1]]:
+// AMDGCNSPIRV-NEXT: [[TMP26:%.*]] = phi i64 [ [[TMP25]], %[[STRLEN_WHILE_DONE3]] ], [ 0, %[[STRLEN_JOIN]] ]
+// AMDGCNSPIRV-NEXT: [[TMP27:%.*]] = call addrspace(4) i64 @__ockl_printf_append_string_n(i64 [[TMP16]], ptr addrspace(4) [[TMP0]], i64 [[TMP26]], i32 0)
+// AMDGCNSPIRV-NEXT: [[TMP28:%.*]] = ptrtoint ptr addrspace(4) [[TMP1]] to i64
+// AMDGCNSPIRV-NEXT: [[TMP29:%.*]] = call addrspace(4) i64 @__ockl_printf_append_args(i64 [[TMP27]], i32 1, i64 [[TMP28]], i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i32 1)
+// AMDGCNSPIRV-NEXT: [[TMP30:%.*]] = trunc i64 [[TMP29]] to i32
+// AMDGCNSPIRV-NEXT: ret i32 [[TMP30]]
+//
__device__ int foo1() {
const char *s = "hello world";
return printf("%.*f %*.*s %p\n", 8, 3.14159, 8, 4, s, s);
}
-// CHECK-LABEL: @_Z4foo1v()
-// CHECK: [[BEGIN:%.*]] = call i64 @__ockl_printf_begin(i64 0)
-// CHECK: [[STRLEN1:%.*]] = phi i64 [ %{{[^,]*}}, %{{[^ ]*}} ], [ 0, %{{[^ ]*}} ]
-// CHECK: [[APPEND1:%.*]] = call i64 @__ockl_printf_append_string_n(i64 [[BEGIN]], {{.*}}, i64 [[STRLEN1]], i32 0)
-// CHECK: [[APPEND2:%.*]] = call i64 @__ockl_printf_append_args(i64 [[APPEND1]], i32 1, i64 8, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i32 0)
-// CHECK: [[APPEND3:%.*]] = call i64 @__ockl_printf_append_args(i64 [[APPEND2]], i32 1, i64 4614256650576692846, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i32 0)
-// CHECK: [[APPEND4:%.*]] = call i64 @__ockl_printf_append_args(i64 [[APPEND3]], i32 1, i64 8, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i32 0)
-// CHECK: [[APPEND5:%.*]] = call i64 @__ockl_printf_append_args(i64 [[APPEND4]], i32 1, i64 4, i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i32 0)
-// CHECK: [[STRLEN2:%.*]] = phi i64 [ %{{[^,]*}}, %{{[^ ]*}} ], [ 0, %{{[^ ]*}} ]
-// CHECK: [[APPEND6:%.*]] = call i64 @__ockl_printf_append_string_n(i64 [[APPEND5]], {{.*}}, i64 [[STRLEN2]], i32 0)
-// CHECK: [[PTR2INT:%.*]] = ptrtoint ptr %{{.*}} to i64
-// CHECK: [[APPEND7:%.*]] = call i64 @__ockl_printf_append_args(i64 [[APPEND6]], i32 1, i64 [[PTR2INT]], i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i32 1)
-// CHECK: [[RETURN:%.*]] = trunc i64 [[APPEND7]] to i32
-// CHECK: ret i32 [[RETURN]]
-
__device__ char *dstr;
+// AMDGCN-LABEL: define dso_local noundef i32 @_Z4foo2v(
+// AMDGCN-SAME: ) #[[ATTR0:[0-9]+]] {
+// AMDGCN-NEXT: [[ENTRY:.*]]:
+// AMDGCN-NEXT: [[RETVAL:%.*]] = alloca i32, align 4, addrspace(5)
+// AMDGCN-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[RETVAL]] to ptr
+// AMDGCN-NEXT: [[TMP0:%.*]] = load ptr, ptr addrspacecast (ptr addrspace(1) @dstr to ptr), align 8
+// AMDGCN-NEXT: [[TMP1:%.*]] = load ptr, ptr addrspacecast (ptr addrspace(1) @dstr to ptr), align 8
+// AMDGCN-NEXT: [[TMP2:%.*]] = call i64 @__ockl_printf_begin(i64 0)
+// AMDGCN-NEXT: [[TMP3:%.*]] = icmp eq ptr addrspacecast (ptr addrspace(4) @.str.2 to ptr), null
+// AMDGCN-NEXT: br i1 [[TMP3]], label %[[STRLEN_JOIN:.*]], label %[[STRLEN_WHILE:.*]]
+// AMDGCN: [[STRLEN_WHILE]]:
+// AMDGCN-NEXT: [[TMP4:%.*]] = phi ptr [ addrspacecast (ptr addrspace(4) @.str.2 to ptr), %[[ENTRY]] ], [ [[TMP5:%.*]], %[[STRLEN_WHILE]] ]
+// AMDGCN-NEXT: [[TMP5]] = getelementptr i8, ptr [[TMP4]], i64 1
+// AMDGCN-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP4]], align 1
+// AMDGCN-NEXT: [[TMP7:%.*]] = icmp eq i8 [[TMP6]], 0
+// AMDGCN-NEXT: br i1 [[TMP7]], label %[[STRLEN_WHILE_DONE:.*]], label %[[STRLEN_WHILE]]
+// AMDGCN: [[STRLEN_WHILE_DONE]]:
+// AMDGCN-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP4]] to i64
+// AMDGCN-NEXT: [[TMP9:%.*]] = sub i64 [[TMP8]], ptrtoint (ptr addrspacecast (ptr addrspace(4) @.str.2 to ptr) to i64)
+// AMDGCN-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], 1
+// AMDGCN-NEXT: br label %[[STRLEN_JOIN]]
+// AMDGCN: [[STRLEN_JOIN]]:
+// AMDGCN-NEXT: [[TMP11:%.*]] = phi i64 [ [[TMP10]], %[[STRLEN_WHILE_DONE]] ], [ 0, %[[ENTRY]] ]
+// AMDGCN-NEXT: [[TMP12:%.*]] = call i64 @__ockl_printf_append_string_n(i64 [[TMP2]], ptr addrspacecast (ptr addrspace(4) @.str.2 to ptr), i64 [[TMP11]], i32 0)
+// AMDGCN-NEXT: [[TMP13:%.*]] = icmp eq ptr [[TMP0]], null
+// AMDGCN-NEXT: br i1 [[TMP13]], label %[[STRLEN_JOIN1:.*]], label %[[STRLEN_WHILE2:.*]]
+// AMDGCN: [[STRLEN_WHILE2]]:
+// AMDGCN-NEXT: [[TMP14:%.*]] = phi ptr [ [[TMP0]], %[[STRLEN_JOIN]] ], [ [[TMP15:%.*]], %[[STRLEN_WHILE2]] ]
+// AMDGCN-NEXT: [[TMP15]] = getelementptr i8, ptr [[TMP14]], i64 1
+// AMDGCN-NEXT: [[TMP16:%.*]] = load i8, ptr [[TMP14]], align 1
+// AMDGCN-NEXT: [[TMP17:%.*]] = icmp eq i8 [[TMP16]], 0
+// AMDGCN-NEXT: br i1 [[TMP17]], label %[[STRLEN_WHILE_DONE3:.*]], label %[[STRLEN_WHILE2]]
+// AMDGCN: [[STRLEN_WHILE_DONE3]]:
+// AMDGCN-NEXT: [[TMP18:%.*]] = ptrtoint ptr [[TMP0]] to i64
+// AMDGCN-NEXT: [[TMP19:%.*]] = ptrtoint ptr [[TMP14]] to i64
+// AMDGCN-NEXT: [[TMP20:%.*]] = sub i64 [[TMP19]], [[TMP18]]
+// AMDGCN-NEXT: [[TMP21:%.*]] = add i64 [[TMP20]], 1
+// AMDGCN-NEXT: br label %[[STRLEN_JOIN1]]
+// AMDGCN: [[STRLEN_JOIN1]]:
+// AMDGCN-NEXT: [[TMP22:%.*]] = phi i64 [ [[TMP21]], %[[STRLEN_WHILE_DONE3]] ], [ 0, %[[STRLEN_JOIN]] ]
+// AMDGCN-NEXT: [[TMP23:%.*]] = call i64 @__ockl_printf_append_string_n(i64 [[TMP12]], ptr [[TMP0]], i64 [[TMP22]], i32 0)
+// AMDGCN-NEXT: [[TMP24:%.*]] = ptrtoint ptr [[TMP1]] to i64
+// AMDGCN-NEXT: [[TMP25:%.*]] = call i64 @__ockl_printf_append_args(i64 [[TMP23]], i32 1, i64 [[TMP24]], i64 0, i64 0, i64 0, i64 0, i64 0, i64 0, i32 1)
+// AMDGCN-NEXT: [[TMP26:%.*]] = trunc i64 [[TMP25]] to i32
+// AMDGCN-NEXT: ret i32 [[TMP26]]
+//
+// AMDGCNSPIRV-LABEL: define spir_func noundef i32 @_Z4foo2v(
+// AMDGCNSPIRV-SAME: ) addrspace(4) #[[ATTR0:[0-9]+]] {
+// AMDGCNSPIRV-NEXT: [[ENTRY:.*]]:
+// AMDGCNSPIRV-NEXT: [[RETVAL:%.*]] = alloca i32, align 4
+// AMDGCNSPIRV-NEXT: [[RETVAL_ASCAST:%.*]] = addrspacecast ptr [[RETVAL]] to ptr addrspace(4)
+// AMDGCNSPIRV-NEXT: [[TMP0:%.*]] = load ptr addrspace(4), ptr addrspace(4) addrspacecast (ptr addrspace(1) @dstr to ptr addrspace(4)), align 8
+// AMDGCNSPIRV-NEXT: [[TMP1:%.*]] = load ptr addrspace(4), ptr addrspace(4) addrspacecast (ptr addrspace(1) @dstr to ptr addrspace(4)), align 8
+// AMDGCNSPIRV-NEXT: [[TMP2:%.*]] = call addrspace(4) i64 @__ockl_printf_begin(i64 0)
+// AMDGCNSPIRV-NEXT: [[TMP3:%.*]] = icmp eq ptr addrspace(4) addrspacecast (ptr addrspace(1) @.str.2 to ptr addrspace(4)), null
+// AMDGCNSPIRV-NEXT: br i1 [[TMP3]], label %[[STRLEN_JOIN:.*]], label %[[STRLEN_WHILE:.*]]
+// AMDGCNSPIRV: [[STRLEN_WHILE]]:
+// AMDGCNSPIRV-NEXT: [[TMP4:%.*]] = phi ptr addrspace(4) [ addrspacecast (ptr addrspace(1) @.str.2 to ptr addrspace(4)), %[[ENTRY]] ], [ [[TMP5:%.*]], %[[STRLEN_WHILE]] ]
+// AMDGCNSPIRV-NEXT: [[TMP5]] = getelementptr i8, ptr addrspace(4) [[TMP4]], i64 1
+// AMDGCNSPIRV-NEXT: [[TMP6:%.*]] = load i8, ptr addrspace(4) [[TMP4]], align 1
+// AMDGCNSPIRV-NEXT: [[TMP7:%.*]] = icmp eq i8 [[TMP6]], 0
+// AMDGCNSPIRV-NEXT: br i1 [[TMP7]], label %[[STRLEN_WHILE_DONE:.*]], label %[[STRLEN_WHILE]]
+// AMDGCNSPIRV: [[STRLEN_WHILE_DONE]]:
+// AMDGCNSPIRV-NEXT: [[TMP8:%.*]] = ptrtoint ptr addrspace(4) [[TMP4]] to i64
+// AMDGCNSPIRV-NEXT: [[TMP9:%.*]] = sub i64 [[TMP8]], ptrtoint (ptr addrspace(4) addrspacecast (ptr addr...
[truncated]
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✅ With the latest revision this PR passed the C/C++ code formatter. |
arsenm
reviewed
Jun 29, 2024
| if (getTarget().getTriple().isAMDGCN() && getLangOpts().HIP) | ||
| if ((getTarget().getTriple().isAMDGCN() || | ||
| getTarget().getTriple().isSPIRV()) && | ||
| getLangOpts().HIP) |
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Why doesn't this have the same triple vendor logic as the above openmp case?
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OMP seems to have no triple logic, and just unconditionally forwards to their printf impl if on the device path, so I'm not entirely sure on what the question is probing. If you're asking why we're not unconditionally forwarding in HIP, if compiling for device, I don't quite know, I'm merely re-using what was there. If you're asking why I'm not checking again for the vendor type, and merely checking for SPIR-V, it's because it'd be spurious due to the outer check. If it's none of those, could you please clarify what you mean?
yxsamliu
approved these changes
Jul 2, 2024
|
LLVM Buildbot has detected a new failure on builder Full details are available at: https://lab.llvm.org/buildbot/#/builders/72/builds/839 Here is the relevant piece of the build log for the reference: |
This looks like a fluke, keeping an eye on it nonetheless. |
kbluck
pushed a commit
to kbluck/llvm-project
that referenced
this pull request
Jul 6, 2024
…sa` (llvm#97132) This enables the AMDGPU specific implementation of `printf` when compiling for AMDGCN flavoured SPIR-V, the consequence being that the expansion into ROCDL calls & friends gets expanded before "lowering" to SPIR-V and gets carried through. The only relatively "novel" aspect is that the `callAppendStringN` is simplified to take the type of the passed in arguments, as opposed to querying them from the module. This is a neutral change since the arguments were passed directly to the call, without any attempt to cast them, hence the assumption that the actual types match the formal ones was already baked in.
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This enables the AMDGPU specific implementation of
printfwhen compiling for AMDGCN flavoured SPIR-V, the consequence being that the expansion into ROCDL calls & friends gets expanded before "lowering" to SPIR-V and gets carried through. The only relatively "novel" aspect is that thecallAppendStringNis simplified to take the type of the passed in arguments, as opposed to querying them from the module. This is a neutral change since the arguments were passed directly to the call, without any attempt to cast them, hence the assumption that the actual types match the formal ones was already baked in.