[SelectionDAG] Remove LegalTypes argument from getShiftAmountConstant. #97653
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getShiftAmountTy. This patches removes it from getShiftAmountConstant which is one of the callers of getShiftAmountTy.
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@llvm/pr-subscribers-llvm-selectiondag Author: Craig Topper (topperc) Changes#97645 proposes to remove LegalTypes from getShiftAmountTy. This patches removes it from getShiftAmountConstant which is one of the callers of getShiftAmountTy. Full diff: https://github.com/llvm/llvm-project/pull/97653.diff 4 Files Affected:
diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h
index 7b0e5e7d9504b..8e189e9e8bf86 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAG.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -680,10 +680,8 @@ class SelectionDAG {
bool isTarget = false, bool isOpaque = false);
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL,
bool isTarget = false);
- SDValue getShiftAmountConstant(uint64_t Val, EVT VT, const SDLoc &DL,
- bool LegalTypes = true);
- SDValue getShiftAmountConstant(const APInt &Val, EVT VT, const SDLoc &DL,
- bool LegalTypes = true);
+ SDValue getShiftAmountConstant(uint64_t Val, EVT VT, const SDLoc &DL);
+ SDValue getShiftAmountConstant(const APInt &Val, EVT VT, const SDLoc &DL);
SDValue getVectorIdxConstant(uint64_t Val, const SDLoc &DL,
bool isTarget = false);
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index d81a54d2ecaaa..8b65ea944b2a9 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -9301,11 +9301,10 @@ SDValue DAGCombiner::MatchLoadCombine(SDNode *N) {
return NewLoad;
SDValue ShiftedLoad =
- NeedsZext
- ? DAG.getNode(ISD::SHL, SDLoc(N), VT, NewLoad,
- DAG.getShiftAmountConstant(ZeroExtendedBytes * 8, VT,
- SDLoc(N), LegalOperations))
- : NewLoad;
+ NeedsZext ? DAG.getNode(ISD::SHL, SDLoc(N), VT, NewLoad,
+ DAG.getShiftAmountConstant(ZeroExtendedBytes * 8,
+ VT, SDLoc(N)))
+ : NewLoad;
return DAG.getNode(ISD::BSWAP, SDLoc(N), VT, ShiftedLoad);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 96242305e9eab..9d2deb4b5f511 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1752,16 +1752,16 @@ SDValue SelectionDAG::getIntPtrConstant(uint64_t Val, const SDLoc &DL,
}
SDValue SelectionDAG::getShiftAmountConstant(uint64_t Val, EVT VT,
- const SDLoc &DL, bool LegalTypes) {
+ const SDLoc &DL) {
assert(VT.isInteger() && "Shift amount is not an integer type!");
- EVT ShiftVT = TLI->getShiftAmountTy(VT, getDataLayout(), LegalTypes);
+ EVT ShiftVT = TLI->getShiftAmountTy(VT, getDataLayout());
return getConstant(Val, DL, ShiftVT);
}
SDValue SelectionDAG::getShiftAmountConstant(const APInt &Val, EVT VT,
- const SDLoc &DL, bool LegalTypes) {
+ const SDLoc &DL) {
assert(Val.ult(VT.getScalarSizeInBits()) && "Out of range shift");
- return getShiftAmountConstant(Val.getZExtValue(), VT, DL, LegalTypes);
+ return getShiftAmountConstant(Val.getZExtValue(), VT, DL);
}
SDValue SelectionDAG::getVectorIdxConstant(uint64_t Val, const SDLoc &DL,
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index fdd9f1f461759..a0b6fbc6f353c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1880,8 +1880,8 @@ bool TargetLowering::SimplifyDemandedBits(
Flags.setNoSignedWrap(IsNSW);
Flags.setNoUnsignedWrap(IsNUW);
SDValue NewOp = TLO.DAG.getNode(ISD::TRUNCATE, dl, HalfVT, Op0);
- SDValue NewShiftAmt = TLO.DAG.getShiftAmountConstant(
- ShAmt, HalfVT, dl, TLO.LegalTypes());
+ SDValue NewShiftAmt =
+ TLO.DAG.getShiftAmountConstant(ShAmt, HalfVT, dl);
SDValue NewShift = TLO.DAG.getNode(ISD::SHL, dl, HalfVT, NewOp,
NewShiftAmt, Flags);
SDValue NewExt =
@@ -1977,8 +1977,8 @@ bool TargetLowering::SimplifyDemandedBits(
((InDemandedMask.countLeadingZeros() >= (BitWidth / 2)) ||
TLO.DAG.MaskedValueIsZero(Op0, HiBits))) {
SDValue NewOp = TLO.DAG.getNode(ISD::TRUNCATE, dl, HalfVT, Op0);
- SDValue NewShiftAmt = TLO.DAG.getShiftAmountConstant(
- ShAmt, HalfVT, dl, TLO.LegalTypes());
+ SDValue NewShiftAmt =
+ TLO.DAG.getShiftAmountConstant(ShAmt, HalfVT, dl);
SDValue NewShift =
TLO.DAG.getNode(ISD::SRL, dl, HalfVT, NewOp, NewShiftAmt);
return TLO.CombineTo(
@@ -2600,8 +2600,7 @@ bool TargetLowering::SimplifyDemandedBits(
if (!(HighBits & DemandedBits)) {
// None of the shifted in bits are needed. Add a truncate of the
// shift input, then shift it.
- SDValue NewShAmt =
- TLO.DAG.getShiftAmountConstant(ShVal, VT, dl, TLO.LegalTypes());
+ SDValue NewShAmt = TLO.DAG.getShiftAmountConstant(ShVal, VT, dl);
SDValue NewTrunc =
TLO.DAG.getNode(ISD::TRUNCATE, dl, VT, Src.getOperand(0));
return TLO.CombineTo(
@@ -4254,8 +4253,7 @@ SDValue TargetLowering::foldSetCCWithBinOp(EVT VT, SDValue N0, SDValue N1,
return SDValue();
// (X - Y) == Y --> X == Y << 1
- SDValue One =
- DAG.getShiftAmountConstant(1, OpVT, DL, !DCI.isBeforeLegalize());
+ SDValue One = DAG.getShiftAmountConstant(1, OpVT, DL);
SDValue YShl1 = DAG.getNode(ISD::SHL, DL, N1.getValueType(), Y, One);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(YShl1.getNode());
@@ -5113,8 +5111,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
return DAG.getNode(
ISD::TRUNCATE, dl, VT,
DAG.getNode(ISD::SRL, dl, ShValTy, N0,
- DAG.getShiftAmountConstant(
- ShCt, ShValTy, dl, !DCI.isBeforeLegalize())));
+ DAG.getShiftAmountConstant(ShCt, ShValTy, dl)));
}
} else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) {
// (X & 8) == 8 --> (X & 8) >> 3
@@ -5125,8 +5122,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
return DAG.getNode(
ISD::TRUNCATE, dl, VT,
DAG.getNode(ISD::SRL, dl, ShValTy, N0,
- DAG.getShiftAmountConstant(
- ShCt, ShValTy, dl, !DCI.isBeforeLegalize())));
+ DAG.getShiftAmountConstant(ShCt, ShValTy, dl)));
}
}
}
@@ -5144,8 +5140,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
if (!TLI.shouldAvoidTransformToShift(ShValTy, ShiftBits)) {
SDValue Shift = DAG.getNode(
ISD::SRL, dl, ShValTy, N0.getOperand(0),
- DAG.getShiftAmountConstant(ShiftBits, ShValTy, dl,
- !DCI.isBeforeLegalize()));
+ DAG.getShiftAmountConstant(ShiftBits, ShValTy, dl));
SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, ShValTy);
return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
}
@@ -5174,8 +5169,7 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
!TLI.shouldAvoidTransformToShift(ShValTy, ShiftBits)) {
SDValue Shift =
DAG.getNode(ISD::SRL, dl, ShValTy, N0,
- DAG.getShiftAmountConstant(ShiftBits, ShValTy, dl,
- !DCI.isBeforeLegalize()));
+ DAG.getShiftAmountConstant(ShiftBits, ShValTy, dl));
SDValue CmpRHS = DAG.getConstant(NewC, dl, ShValTy);
return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
}
@@ -9599,9 +9593,8 @@ TargetLowering::scalarizeVectorLoad(LoadSDNode *LD,
for (unsigned Idx = 0; Idx < NumElem; ++Idx) {
unsigned ShiftIntoIdx =
(DAG.getDataLayout().isBigEndian() ? (NumElem - 1) - Idx : Idx);
- SDValue ShiftAmount =
- DAG.getShiftAmountConstant(ShiftIntoIdx * SrcEltVT.getSizeInBits(),
- LoadVT, SL, /*LegalTypes=*/false);
+ SDValue ShiftAmount = DAG.getShiftAmountConstant(
+ ShiftIntoIdx * SrcEltVT.getSizeInBits(), LoadVT, SL);
SDValue ShiftedElt = DAG.getNode(ISD::SRL, SL, LoadVT, Load, ShiftAmount);
SDValue Elt =
DAG.getNode(ISD::AND, SL, LoadVT, ShiftedElt, SrcEltBitMask);
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#97645 has landed so this flag no longer does anything. The patch itself is just a mechanical code update. I only posted for review to stage the changes. |
kbluck
pushed a commit
to kbluck/llvm-project
that referenced
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Jul 6, 2024
llvm#97653) llvm#97645 proposed to remove LegalTypes from getShiftAmountTy. This patches removes it from getShiftAmountConstant which is one of the callers of getShiftAmountTy.
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#97645 proposes to remove LegalTypes from getShiftAmountTy. This patches removes it from getShiftAmountConstant which is one of the callers of getShiftAmountTy.