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[RISCV] vsetvl pseudo may cross inline asm without sideeffect #97794

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[RISCV] vsetvl pseudo may cross inline asm without sideeffect #97794

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BeMg Jul 5, 2024
4014893
[RISCV] Add hasSideEffects=1 to vsetvl pseudos
BeMg Jul 5, 2024
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4 changes: 1 addition & 3 deletions llvm/lib/Target/RISCV/RISCVDeadRegisterDefinitions.cpp
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Expand Up @@ -72,9 +72,7 @@ bool RISCVDeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
// are reserved for HINT instructions.
const MCInstrDesc &Desc = MI.getDesc();
if (!Desc.mayLoad() && !Desc.mayStore() &&
!Desc.hasUnmodeledSideEffects() &&
MI.getOpcode() != RISCV::PseudoVSETVLI &&
MI.getOpcode() != RISCV::PseudoVSETIVLI)
!Desc.hasUnmodeledSideEffects())
continue;
// For PseudoVSETVLIX0, Rd = X0 has special meaning.
if (MI.getOpcode() == RISCV::PseudoVSETVLIX0)
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2 changes: 1 addition & 1 deletion llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
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Expand Up @@ -6011,7 +6011,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 0,
//===----------------------------------------------------------------------===//

// Pseudos.
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Defs = [VL, VTYPE] in {
let hasSideEffects = 1, mayLoad = 0, mayStore = 0, Defs = [VL, VTYPE] in {
// Due to rs1=X0 having special meaning, we need a GPRNoX0 register class for
// the when we aren't using one of the special X0 encodings. Otherwise it could
// be accidentally be made X0 by MachineIR optimizations. To satisfy the
Expand Down
37 changes: 37 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/vsetvl-cross-inline-asm.ll
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@@ -0,0 +1,37 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=riscv64 -mcpu=sifive-x280 -verify-machineinstrs < %s | FileCheck %s

define void @foo(<vscale x 8 x half> %0, <vscale x 8 x half> %1) {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: lui a0, 1
; CHECK-NEXT: addiw a0, a0, -1096
; CHECK-NEXT: vmv.v.i v12, 0
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
; CHECK-NEXT: #APP
; CHECK-NEXT: vfmadd.vv v16, v12, v12
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: #APP
; CHECK-NEXT: vfmadd.vv v16, v12, v12
; CHECK-NEXT: #NO_APP
; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
; CHECK-NEXT: vse16.v v8, (zero)
; CHECK-NEXT: ret
entry:
%2 = tail call i64 @llvm.riscv.vsetvli.i64(i64 3000, i64 0, i64 0)
%3 = tail call <vscale x 8 x float> asm sideeffect "vfmadd.vv $0, $1, $2", "=^vr,^vr,^vr,0"(<vscale x 8 x float> zeroinitializer, <vscale x 8 x float> zeroinitializer, <vscale x 8 x float> zeroinitializer)
%4 = tail call <vscale x 8 x float> asm sideeffect "vfmadd.vv $0, $1, $2", "=^vr,^vr,^vr,0"(<vscale x 8 x float> zeroinitializer, <vscale x 8 x float> zeroinitializer, <vscale x 8 x float> %3)
tail call void @llvm.riscv.vse.nxv8f16.i64(<vscale x 8 x half> %0, ptr null, i64 %2)
ret void
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)
declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) #0

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
declare void @llvm.riscv.vse.nxv8f16.i64(<vscale x 8 x half>, ptr nocapture, i64) #1

attributes #0 = { nocallback nofree nosync nounwind willreturn memory(none) }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }
37 changes: 19 additions & 18 deletions llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
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Expand Up @@ -242,6 +242,7 @@ define <vscale x 1 x double> @test6(i64 %avl, i8 zeroext %cond, <vscale x 1 x do
; CHECK-NEXT: andi a1, a1, 2
; CHECK-NEXT: beqz a1, .LBB5_4
; CHECK-NEXT: .LBB5_2: # %if.then4
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: lui a1, %hi(.LCPI5_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI5_0)
; CHECK-NEXT: vlse64.v v9, (a1), zero
Expand Down Expand Up @@ -631,22 +632,22 @@ declare <vscale x 2 x i32> @llvm.riscv.vwadd.w.nxv2i32.nxv2i16(<vscale x 2 x i32
define void @vlmax(i64 %N, ptr %c, ptr %a, ptr %b) {
; CHECK-LABEL: vlmax:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a6, zero, e64, m1, ta, ma
; CHECK-NEXT: blez a0, .LBB12_3
; CHECK-NEXT: # %bb.1: # %for.body.preheader
; CHECK-NEXT: li a4, 0
; CHECK-NEXT: vsetvli a6, zero, e64, m1, ta, ma
; CHECK-NEXT: slli a5, a6, 3
; CHECK-NEXT: li a5, 0
; CHECK-NEXT: slli a4, a6, 3
; CHECK-NEXT: .LBB12_2: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vle64.v v8, (a2)
; CHECK-NEXT: vle64.v v9, (a3)
; CHECK-NEXT: vfadd.vv v8, v8, v9
; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: add a4, a4, a6
; CHECK-NEXT: add a1, a1, a5
; CHECK-NEXT: add a3, a3, a5
; CHECK-NEXT: add a2, a2, a5
; CHECK-NEXT: blt a4, a0, .LBB12_2
; CHECK-NEXT: add a5, a5, a6
; CHECK-NEXT: add a1, a1, a4
; CHECK-NEXT: add a3, a3, a4
; CHECK-NEXT: add a2, a2, a4
; CHECK-NEXT: blt a5, a0, .LBB12_2
; CHECK-NEXT: .LBB12_3: # %for.end
; CHECK-NEXT: ret
entry:
Expand Down Expand Up @@ -678,18 +679,18 @@ for.end: ; preds = %for.body, %entry
define void @vector_init_vlmax(i64 %N, ptr %c) {
; CHECK-LABEL: vector_init_vlmax:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, ma
; CHECK-NEXT: blez a0, .LBB13_3
; CHECK-NEXT: # %bb.1: # %for.body.preheader
; CHECK-NEXT: li a2, 0
; CHECK-NEXT: vsetvli a3, zero, e64, m1, ta, ma
; CHECK-NEXT: slli a4, a3, 3
; CHECK-NEXT: li a3, 0
; CHECK-NEXT: slli a4, a2, 3
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: .LBB13_2: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: add a3, a3, a2
; CHECK-NEXT: add a1, a1, a4
; CHECK-NEXT: blt a2, a0, .LBB13_2
; CHECK-NEXT: blt a3, a0, .LBB13_2
; CHECK-NEXT: .LBB13_3: # %for.end
; CHECK-NEXT: ret
entry:
Expand All @@ -714,20 +715,20 @@ for.end: ; preds = %for.body, %entry
define void @vector_init_vsetvli_N(i64 %N, ptr %c) {
; CHECK-LABEL: vector_init_vsetvli_N:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, a0, e64, m1, ta, ma
; CHECK-NEXT: blez a0, .LBB14_3
; CHECK-NEXT: # %bb.1: # %for.body.preheader
; CHECK-NEXT: li a2, 0
; CHECK-NEXT: vsetvli a3, a0, e64, m1, ta, ma
; CHECK-NEXT: slli a4, a3, 3
; CHECK-NEXT: li a3, 0
; CHECK-NEXT: slli a4, a2, 3
; CHECK-NEXT: vsetvli a5, zero, e64, m1, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: .LBB14_2: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; CHECK-NEXT: vse64.v v8, (a1)
; CHECK-NEXT: add a2, a2, a3
; CHECK-NEXT: add a3, a3, a2
; CHECK-NEXT: add a1, a1, a4
; CHECK-NEXT: blt a2, a0, .LBB14_2
; CHECK-NEXT: blt a3, a0, .LBB14_2
; CHECK-NEXT: .LBB14_3: # %for.end
; CHECK-NEXT: ret
entry:
Expand Down
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