[CodeGen] Use range-based for loops (NFC)

llvm/lib/CodeGen/InterferenceCache.cpp

@@ -136,14 +136,12 @@ void InterferenceCache::Entry::update(unsigned MBBNum) {
   // Use advanceTo only when possible.
   if (PrevPos != Start) {
     if (!PrevPos.isValid() || Start < PrevPos) {
-      for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
-        RegUnitInfo &RUI = RegUnits[i];
+      for (RegUnitInfo &RUI : RegUnits) {
         RUI.VirtI.find(Start);
         RUI.FixedI = RUI.Fixed->find(Start);
       }
     } else {
-      for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
-        RegUnitInfo &RUI = RegUnits[i];
+      for (RegUnitInfo &RUI : RegUnits) {
         RUI.VirtI.advanceTo(Start);
         if (RUI.FixedI != RUI.Fixed->end())
           RUI.FixedI = RUI.Fixed->advanceTo(RUI.FixedI, Start);
@@ -162,8 +160,8 @@ void InterferenceCache::Entry::update(unsigned MBBNum) {
     BI->First = BI->Last = SlotIndex();
 
     // Check for first interference from virtregs.
-    for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
-      LiveIntervalUnion::SegmentIter &I = RegUnits[i].VirtI;
+    for (RegUnitInfo &RUI : RegUnits) {
+      LiveIntervalUnion::SegmentIter &I = RUI.VirtI;
       if (!I.valid())
         continue;
       SlotIndex StartI = I.start();
@@ -174,9 +172,9 @@ void InterferenceCache::Entry::update(unsigned MBBNum) {
     }
 
     // Same thing for fixed interference.
-    for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
-      LiveInterval::const_iterator I = RegUnits[i].FixedI;
-      LiveInterval::const_iterator E = RegUnits[i].Fixed->end();
+    for (RegUnitInfo &RUI : RegUnits) {
+      LiveInterval::const_iterator I = RUI.FixedI;
+      LiveInterval::const_iterator E = RUI.Fixed->end();
       if (I == E)
         continue;
       SlotIndex StartI = I->start;
@@ -213,8 +211,8 @@ void InterferenceCache::Entry::update(unsigned MBBNum) {
   }
 
   // Check for last interference in block.
-  for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
-    LiveIntervalUnion::SegmentIter &I = RegUnits[i].VirtI;
+  for (RegUnitInfo &RUI : RegUnits) {
+    LiveIntervalUnion::SegmentIter &I = RUI.VirtI;
     if (!I.valid() || I.start() >= Stop)
       continue;
     I.advanceTo(Stop);
@@ -229,9 +227,9 @@ void InterferenceCache::Entry::update(unsigned MBBNum) {
   }
 
   // Fixed interference.
-  for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
-    LiveInterval::iterator &I = RegUnits[i].FixedI;
-    LiveRange *LR = RegUnits[i].Fixed;
+  for (RegUnitInfo &RUI : RegUnits) {
+    LiveInterval::iterator &I = RUI.FixedI;
+    LiveRange *LR = RUI.Fixed;
     if (I == LR->end() || I->start >= Stop)
       continue;
     I = LR->advanceTo(I, Stop);

llvm/lib/CodeGen/LiveIntervals.cpp

@@ -1536,8 +1536,7 @@ void LiveIntervals::handleMoveIntoNewBundle(MachineInstr &BundleStart,
 
   // Fix up dead defs
   const SlotIndex Index = getInstructionIndex(BundleStart);
-  for (unsigned Idx = 0, E = BundleStart.getNumOperands(); Idx != E; ++Idx) {
-    MachineOperand &MO = BundleStart.getOperand(Idx);
+  for (MachineOperand &MO : BundleStart.operands()) {
     if (!MO.isReg())
       continue;
     Register Reg = MO.getReg();

llvm/lib/CodeGen/MachineConvergenceVerifier.cpp

@@ -51,8 +51,7 @@ GenericConvergenceVerifier<MachineSSAContext>::findAndCheckConvergenceTokenUsed(
   const MachineRegisterInfo &MRI = Context.getFunction()->getRegInfo();
   const MachineInstr *TokenDef = nullptr;
 
-  for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
-    const MachineOperand &MO = MI.getOperand(I);
+  for (const MachineOperand &MO : MI.operands()) {
     if (!MO.isReg() || !MO.isUse())
       continue;
     Register OpReg = MO.getReg();

llvm/lib/CodeGen/MachineInstr.cpp

@@ -1041,8 +1041,7 @@ unsigned MachineInstr::getBundleSize() const {
 /// Returns true if the MachineInstr has an implicit-use operand of exactly
 /// the given register (not considering sub/super-registers).
 bool MachineInstr::hasRegisterImplicitUseOperand(Register Reg) const {
-  for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
-    const MachineOperand &MO = getOperand(i);
+  for (const MachineOperand &MO : operands()) {
     if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
       return true;
   }