[llvm] Fix typos in target features' descriptions #98259
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@llvm/pr-subscribers-backend-risc-v @llvm/pr-subscribers-backend-arm Author: Jora Troosh (tensorush) ChangesUpstreaming typo fixes from here: Full diff: https://github.com/llvm/llvm-project/pull/98259.diff 4 Files Affected:
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index 8754ea4974999..685caab5cbf1f 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -194,7 +194,7 @@ def FeatureComplxNum : ExtensionWithMArch<"complxnum", "ComplxNum", "FEAT_FCMA",
[FeatureNEON]>;
def FeatureNV : Extension<"nv", "NV", "FEAT_NV, FEAT_NV2",
- "Enable v8.4-A Nested Virtualization Enchancement">;
+ "Enable v8.4-A Nested Virtualization Enhancement">;
//===----------------------------------------------------------------------===//
// Armv8.4 Architecture Extensions
@@ -467,10 +467,10 @@ def FeatureFAMINMAX: ExtensionWithMArch<"faminmax", "FAMINMAX", "FEAT_FAMINMAX",
def FeatureLUT: ExtensionWithMArch<"lut", "LUT", "FEAT_LUT",
"Enable Lookup Table instructions">;
-
+
def FeatureFP8 : ExtensionWithMArch<"fp8", "FP8", "FEAT_FP8",
"Enable FP8 instructions", [FeatureFAMINMAX, FeatureLUT, FeatureBF16]>;
-
+
def FeatureFP8FMA : ExtensionWithMArch<"fp8fma", "FP8FMA", "FEAT_FP8FMA",
"Enable fp8 multiply-add instructions", [FeatureFP8]>;
@@ -479,7 +479,7 @@ def FeatureSSVE_FP8FMA : ExtensionWithMArch<"ssve-fp8fma", "SSVE_FP8FMA", "FEAT_
def FeatureFP8DOT4: ExtensionWithMArch<"fp8dot4", "FP8DOT4", "FEAT_FP8DOT4",
"Enable fp8 4-way dot instructions", [FeatureFP8FMA]>;
-
+
def FeatureFP8DOT2: ExtensionWithMArch<"fp8dot2", "FP8DOT2", "FEAT_FP8DOT2",
"Enable fp8 2-way dot instructions", [FeatureFP8DOT4]>;
diff --git a/llvm/lib/Target/ARM/ARMFeatures.td b/llvm/lib/Target/ARM/ARMFeatures.td
index 8b0ade54b46d3..5fbe14d08edc5 100644
--- a/llvm/lib/Target/ARM/ARMFeatures.td
+++ b/llvm/lib/Target/ARM/ARMFeatures.td
@@ -523,11 +523,11 @@ def FeatureLOB : SubtargetFeature<"lob", "HasLOB", "true",
"Enable Low Overhead Branch "
"extensions">;
-// Mitigate against the cve-2021-35465 security vulnurability.
+// Mitigate against the cve-2021-35465 security vulnerability.
def FeatureFixCMSE_CVE_2021_35465 : SubtargetFeature<"fix-cmse-cve-2021-35465",
"FixCMSE_CVE_2021_35465", "true",
"Mitigate against the cve-2021-35465 "
- "security vulnurability">;
+ "security vulnerability">;
def FeaturePACBTI : SubtargetFeature<"pacbti", "HasPACBTI", "true",
"Enable Pointer Authentication and Branch "
@@ -761,4 +761,3 @@ def FeatureHardenSlsNoComdat : SubtargetFeature<"harden-sls-nocomdat",
def ModeBigEndianInstructions : SubtargetFeature<"big-endian-instructions",
"BigEndianInstructions", "true",
"Expect instructions to be stored big-endian.">;
-
diff --git a/llvm/lib/Target/CSKY/CSKY.td b/llvm/lib/Target/CSKY/CSKY.td
index 9809caa8bd8f6..f88daeed8d421 100644
--- a/llvm/lib/Target/CSKY/CSKY.td
+++ b/llvm/lib/Target/CSKY/CSKY.td
@@ -97,28 +97,28 @@ def iHasFLOAT7E60 : Predicate<"Subtarget->hasFLOAT7E60()">,
"Support CSKY float7e60 instructions">;
def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
- "Enable divide instrutions">;
+ "Enable divide instructions">;
def HasHWDiv : Predicate<"Subtarget->hasHardwareDivide()">,
AssemblerPredicate<(all_of FeatureHWDiv),
- "Enable divide instrutions">;
+ "Enable divide instructions">;
def FeatureSTM : SubtargetFeature<"multiple_stld", "HasSTM", "true",
- "Enable multiple load/store instrutions">;
+ "Enable multiple load/store instructions">;
def HasSTM : Predicate<"Subtarget->hasSTM()">,
AssemblerPredicate<(all_of FeatureSTM),
- "Enable multiple load/store instrutions">;
+ "Enable multiple load/store instructions">;
def FeaturePushPop : SubtargetFeature<"pushpop", "HasPushPop", "true",
- "Enable push/pop instrutions">;
+ "Enable push/pop instructions">;
def HasPushPop : Predicate<"Subtarget->hasPushPop()">,
AssemblerPredicate<(all_of FeaturePushPop),
- "Enable push/pop instrutions">;
+ "Enable push/pop instructions">;
def FeatureDSP
- : SubtargetFeature<"edsp", "HasDSP", "true", "Enable DSP instrutions">;
+ : SubtargetFeature<"edsp", "HasDSP", "true", "Enable DSP instructions">;
def HasDSP : Predicate<"Subtarget->hasDSP()">,
AssemblerPredicate<(all_of FeatureDSP),
- "Enable DSP instrutions">;
+ "Enable DSP instructions">;
def HasDSP1E2
: SubtargetFeature<"dsp1e2", "HasDSP1E2", "true", "Support CSKY dsp1e2 instructions">;
@@ -133,16 +133,16 @@ def iHasDSPE60 : Predicate<"Subtarget->hasDSPE60()">,
"Support CSKY dspe60 instructions">;
def FeatureDSPV2 : SubtargetFeature<"dspv2", "HasDSPV2", "true",
- "Enable DSP V2.0 instrutions">;
+ "Enable DSP V2.0 instructions">;
def HasDSPV2 : Predicate<"Subtarget->hasDSPV2()">,
AssemblerPredicate<(all_of FeatureDSPV2),
- "Enable DSP V2.0 instrutions">;
+ "Enable DSP V2.0 instructions">;
def FeatureDSP_Silan : SubtargetFeature<"dsp_silan", "HasDSP_Silan", "true",
- "Enable DSP Silan instrutions">;
+ "Enable DSP Silan instructions">;
def HasDSP_Silan : Predicate<"Subtarget->hasDSP_Silan()">,
AssemblerPredicate<(all_of FeatureDSP_Silan),
- "Enable DSP Silan instrutions">;
+ "Enable DSP Silan instructions">;
// Atomic Support
def FeatureBTST16 : SubtargetFeature<"btst16", "HasBTST16", "true",
@@ -232,11 +232,11 @@ def FeatureSoftTP : SubtargetFeature<"soft-tp", "ReadTPHard", "false",
"Disable TLS Pointer register">;
def FeatureIstack : SubtargetFeature<"istack", "EnableInterruptAttribute",
- "true", "Enable interrput attribute">;
+ "true", "Enable interrupt attribute">;
def EnableInterruptAttribute
: Predicate<"Subtarget->enableInterruptAttribute()">,
AssemblerPredicate<(all_of FeatureIstack),
- "Enable interrput attribute">;
+ "Enable interrupt attribute">;
def FeatureConstPool : SubtargetFeature<"constpool", "DumpConstPool", "true",
"Dump the constant pool by compiler">;
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index e2a8fb485850f..72d01f1258013 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -406,19 +406,19 @@ def FeatureStdExtZcf
def FeatureStdExtZcmp
: RISCVExtension<"zcmp", 1, 0,
- "'Zcmp' (sequenced instuctions for code-size reduction)",
+ "'Zcmp' (sequenced instructions for code-size reduction)",
[FeatureStdExtZca]>;
def HasStdExtZcmp : Predicate<"Subtarget->hasStdExtZcmp() && !Subtarget->hasStdExtC()">,
AssemblerPredicate<(all_of FeatureStdExtZcmp),
- "'Zcmp' (sequenced instuctions for code-size reduction)">;
+ "'Zcmp' (sequenced instructions for code-size reduction)">;
def FeatureStdExtZcmt
: RISCVExtension<"zcmt", 1, 0,
- "'Zcmt' (table jump instuctions for code-size reduction)",
+ "'Zcmt' (table jump instructions for code-size reduction)",
[FeatureStdExtZca, FeatureStdExtZicsr]>;
def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">,
AssemblerPredicate<(all_of FeatureStdExtZcmt),
- "'Zcmt' (table jump instuctions for code-size reduction)">;
+ "'Zcmt' (table jump instructions for code-size reduction)">;
def FeatureStdExtZce
: RISCVExtension<"zce", 1, 0,
|
wangpc-pp
approved these changes
Jul 10, 2024
topperc
reviewed
Jul 10, 2024
| @@ -406,19 +406,19 @@ def FeatureStdExtZcf | |||
|
|
|||
| def FeatureStdExtZcmp | |||
| : RISCVExtension<"zcmp", 1, 0, | |||
| "'Zcmp' (sequenced instuctions for code-size reduction)", | |||
| "'Zcmp' (sequenced instructions for code-size reduction)", | |||
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This text appears in a test file generated from this. I'll fix it and make a commit.
topperc
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Jul 10, 2024
Taken from #98259 and with the necessary test updates added.
davemgreen
reviewed
Jul 10, 2024
DavidSpickett
changed the title
aaryanshukla
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to aaryanshukla/llvm-project
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Jul 14, 2024
Taken from llvm#98259 and with the necessary test updates added.
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Upstreaming typo fixes from here:
ziglang/zig#20560 (comment)