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[AArch64] Improve the codegen for sdiv 2 #98324

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Merged
merged 1 commit into from
Jul 12, 2024
Merged

[AArch64] Improve the codegen for sdiv 2 #98324

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6 changes: 6 additions & 0 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -17747,6 +17747,12 @@ AArch64TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
!(Divisor.isPowerOf2() || Divisor.isNegatedPowerOf2()))
return SDValue();

// If the divisor is 2 or -2, the default expansion is better. It will add
// (N->getValueType(0) >> (BitWidth - 1)) to it before shifting right.
if (Divisor == 2 ||
Divisor == APInt(Divisor.getBitWidth(), -2, /*isSigned*/ true))
return SDValue();

return TargetLowering::buildSDIVPow2WithCMov(N, Divisor, DAG, Created);
}

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3 changes: 1 addition & 2 deletions llvm/test/CodeGen/AArch64/aarch64-bit-gen.ll
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Expand Up @@ -202,9 +202,8 @@ define <4 x i32> @test_bit_sink_operand(<4 x i32> %src, <4 x i32> %dst, <4 x i32
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: sub sp, sp, #32
; CHECK-SD-NEXT: .cfi_def_cfa_offset 32
; CHECK-SD-NEXT: cmp w0, #0
; CHECK-SD-NEXT: add w8, w0, w0, lsr #31
; CHECK-SD-NEXT: mov w9, wzr
; CHECK-SD-NEXT: cinc w8, w0, lt
; CHECK-SD-NEXT: asr w8, w8, #1
; CHECK-SD-NEXT: .LBB11_1: // %do.body
; CHECK-SD-NEXT: // =>This Inner Loop Header: Depth=1
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9 changes: 3 additions & 6 deletions llvm/test/CodeGen/AArch64/sdivpow2.ll
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Expand Up @@ -90,8 +90,7 @@ define i64 @test7(i64 %x) {
define i64 @test8(i64 %x) {
; ISEL-LABEL: test8:
; ISEL: // %bb.0:
; ISEL-NEXT: cmp x0, #0
; ISEL-NEXT: cinc x8, x0, lt
; ISEL-NEXT: add x8, x0, x0, lsr #63
; ISEL-NEXT: asr x0, x8, #1
; ISEL-NEXT: ret
;
Expand All @@ -110,10 +109,8 @@ define i32 @sdiv_int(i32 %begin, i32 %first) #0 {
; ISEL-LABEL: sdiv_int:
; ISEL: // %bb.0:
; ISEL-NEXT: sub w8, w0, w1
; ISEL-NEXT: add w9, w8, #1
; ISEL-NEXT: add w10, w8, #2
; ISEL-NEXT: cmp w9, #0
; ISEL-NEXT: csinc w8, w10, w8, lt
; ISEL-NEXT: add w8, w8, #1
; ISEL-NEXT: add w8, w8, w8, lsr #31
; ISEL-NEXT: sub w0, w0, w8, asr #1
; ISEL-NEXT: ret
;
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