Skip to content

Allow MAY(R)? to accept the high components of register pairs #98606

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Jul 18, 2024
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
14 changes: 12 additions & 2 deletions llvm/lib/Target/SystemZ/SystemZInstrHFP.td
Original file line number Diff line number Diff line change
Expand Up @@ -209,13 +209,23 @@ def MYH : BinaryRXF<"myh", 0xED3D, null_frag, FP64, FP64, z_load, 8>;
def MYL : BinaryRXF<"myl", 0xED39, null_frag, FP64, FP64, z_load, 8>;

// Fused multiply-add (unnormalized).
def MAYR : TernaryRRD<"mayr", 0xB33A, null_frag, FP128, FP64>;
def MAYHR : TernaryRRD<"mayhr", 0xB33C, null_frag, FP64, FP64>;
def MAYLR : TernaryRRD<"maylr", 0xB338, null_frag, FP64, FP64>;
def MAY : TernaryRXF<"may", 0xED3A, null_frag, FP128, FP64, z_load, 8>;
def MAYH : TernaryRXF<"mayh", 0xED3C, null_frag, FP64, FP64, z_load, 8>;
def MAYL : TernaryRXF<"mayl", 0xED38, null_frag, FP64, FP64, z_load, 8>;

// MAY and MAYR allow the user to specify the floating point register pair
// making up the FP128 register by either the lower-numbered register or the
// higher-numbered register, in contrast to all other floating point
// instructions.
// For this reason, the defs below accept `FP64,FP64` instead of `FP128,FP64`.
// This is ok since these instructions are not used in code generation.
// If and when code generation is enabled, the code gen variants should be
// split out from this and use the proper register classes, while these should
// remain for the Assembler and Disassembler to remain compliant with the POP.
def MAY : TernaryRXF<"may", 0xED3A, null_frag, FP64, FP64, z_load, 8>;
def MAYR : TernaryRRD<"mayr", 0xB33A, null_frag, FP64, FP64>;

// Division.
def DER : BinaryRR <"der", 0x3D, null_frag, FP32, FP32>;
def DDR : BinaryRR <"ddr", 0x2D, null_frag, FP64, FP64>;
Expand Down
8 changes: 0 additions & 8 deletions llvm/test/MC/SystemZ/insn-bad.s
Original file line number Diff line number Diff line change
Expand Up @@ -4176,12 +4176,9 @@
#CHECK: may %f0, %f0, -1
#CHECK: error: invalid operand
#CHECK: may %f0, %f0, 4096
#CHECK: error: invalid register pair
#CHECK: may %f2, %f0, 0

may %f0, %f0, -1
may %f0, %f0, 4096
may %f2, %f0, 0
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Oh, one more thing: in addition to removing the insn-bad error check, can you please add a positive test to insn-good that this is actually accepted? This is quite unusual, and it would be good to have a test that catches any accidental regression here.

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

done


#CHECK: error: invalid operand
#CHECK: mayh %f0, %f0, -1
Expand All @@ -4199,11 +4196,6 @@
mayl %f0, %f0, -1
mayl %f0, %f0, 4096

#CHECK: error: invalid register pair
#CHECK: mayr %f2, %f0, %f0

mayr %f2, %f0, %f0

#CHECK: error: invalid operand
#CHECK: mc -1, 0
#CHECK: error: invalid operand
Expand Down
4 changes: 4 additions & 0 deletions llvm/test/MC/SystemZ/insn-good.s
Original file line number Diff line number Diff line change
Expand Up @@ -11517,6 +11517,7 @@
#CHECK: may %f0, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0x00,0x3a]
#CHECK: may %f13, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0xd0,0x3a]
#CHECK: may %f13, %f15, 0 # encoding: [0xed,0xf0,0x00,0x00,0xd0,0x3a]
#CHECK: may %f2, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x20,0x3a]

may %f0, %f0, 0
may %f0, %f0, 4095
Expand All @@ -11527,6 +11528,7 @@
may %f0, %f15, 0
may %f13, %f0, 0
may %f13, %f15, 0
may %f2, %f0, 0

#CHECK: mayh %f0, %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x3c]
#CHECK: mayh %f0, %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x3c]
Expand Down Expand Up @@ -11602,13 +11604,15 @@
#CHECK: mayr %f13, %f0, %f0 # encoding: [0xb3,0x3a,0xd0,0x00]
#CHECK: mayr %f5, %f8, %f9 # encoding: [0xb3,0x3a,0x50,0x89]
#CHECK: mayr %f13, %f15, %f15 # encoding: [0xb3,0x3a,0xd0,0xff]
#CHECK: mayr %f2, %f0, %f0 # encoding: [0xb3,0x3a,0x20,0x00]

mayr %f0, %f0, %f0
mayr %f0, %f0, %f15
mayr %f0, %f15, %f0
mayr %f13, %f0, %f0
mayr %f5, %f8, %f9
mayr %f13, %f15, %f15
mayr %f2, %f0, %f0

#CHECK: mc 0, 0 # encoding: [0xaf,0x00,0x00,0x00]
#CHECK: mc 4095, 0 # encoding: [0xaf,0x00,0x0f,0xff]
Expand Down
Loading