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[AArch64] Take cmn into account when adjusting compare constants #98634

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Merged
merged 1 commit into from
Jul 16, 2024
Merged

[AArch64] Take cmn into account when adjusting compare constants #98634

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13 changes: 9 additions & 4 deletions llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3870,10 +3870,15 @@ static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
// cmp w13, w12
// can be turned into:
// cmp w12, w11, lsl #1
if (!isa<ConstantSDNode>(RHS) || !isLegalArithImmed(RHS->getAsZExtVal())) {
SDValue TheLHS = isCMN(LHS, CC) ? LHS.getOperand(1) : LHS;

if (getCmpOperandFoldingProfit(TheLHS) > getCmpOperandFoldingProfit(RHS)) {
if (!isa<ConstantSDNode>(RHS) ||
!isLegalArithImmed(RHS->getAsAPIntVal().abs().getZExtValue())) {
bool LHSIsCMN = isCMN(LHS, CC);
bool RHSIsCMN = isCMN(RHS, CC);
SDValue TheLHS = LHSIsCMN ? LHS.getOperand(1) : LHS;
SDValue TheRHS = RHSIsCMN ? RHS.getOperand(1) : RHS;

if (getCmpOperandFoldingProfit(TheLHS) + (LHSIsCMN ? 1 : 0) >
getCmpOperandFoldingProfit(TheRHS) + (RHSIsCMN ? 1 : 0)) {
std::swap(LHS, RHS);
CC = ISD::getSetCCSwappedOperands(CC);
}
Expand Down
40 changes: 20 additions & 20 deletions llvm/test/CodeGen/AArch64/cmp-to-cmn.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@ target triple = "arm64"
define i1 @test_EQ_IllEbT(i64 %a, i64 %b) {
; CHECK-LABEL: test_EQ_IllEbT:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmn x1, x0
; CHECK-NEXT: cmn x0, x1
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
entry:
Expand Down Expand Up @@ -72,7 +72,7 @@ entry:
define i1 @test_EQ_IiiEbT(i32 %a, i32 %b) {
; CHECK-LABEL: test_EQ_IiiEbT:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmn w1, w0
; CHECK-NEXT: cmn w0, w1
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
entry:
Expand Down Expand Up @@ -137,8 +137,8 @@ entry:
define i1 @test_EQ_IssEbT(i16 %a, i16 %b) {
; CHECK-LABEL: test_EQ_IssEbT:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sxth w8, w1
; CHECK-NEXT: cmn w8, w0, sxth
; CHECK-NEXT: sxth w8, w0
; CHECK-NEXT: cmn w8, w1, sxth
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
entry:
Expand All @@ -152,8 +152,8 @@ entry:
define i1 @test_EQ_IscEbT(i16 %a, i8 %b) {
; CHECK-LABEL: test_EQ_IscEbT:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: and w8, w1, #0xff
; CHECK-NEXT: cmn w8, w0, sxth
; CHECK-NEXT: sxth w8, w0
; CHECK-NEXT: cmn w8, w1, uxtb
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
entry:
Expand Down Expand Up @@ -194,8 +194,8 @@ entry:
define i1 @test_EQ_IcsEbT(i8 %a, i16 %b) {
; CHECK-LABEL: test_EQ_IcsEbT:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sxth w8, w1
; CHECK-NEXT: cmn w8, w0, uxtb
; CHECK-NEXT: and w8, w0, #0xff
; CHECK-NEXT: cmn w8, w1, sxth
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
entry:
Expand All @@ -209,8 +209,8 @@ entry:
define i1 @test_EQ_IccEbT(i8 %a, i8 %b) {
; CHECK-LABEL: test_EQ_IccEbT:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: and w8, w1, #0xff
; CHECK-NEXT: cmn w8, w0, uxtb
; CHECK-NEXT: and w8, w0, #0xff
; CHECK-NEXT: cmn w8, w1, uxtb
; CHECK-NEXT: cset w0, eq
; CHECK-NEXT: ret
entry:
Expand All @@ -224,7 +224,7 @@ entry:
define i1 @test_NE_IllEbT(i64 %a, i64 %b) {
; CHECK-LABEL: test_NE_IllEbT:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmn x1, x0
; CHECK-NEXT: cmn x0, x1
; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ret
entry:
Expand Down Expand Up @@ -290,7 +290,7 @@ entry:
define i1 @test_NE_IiiEbT(i32 %a, i32 %b) {
; CHECK-LABEL: test_NE_IiiEbT:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: cmn w1, w0
; CHECK-NEXT: cmn w0, w1
; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ret
entry:
Expand Down Expand Up @@ -355,8 +355,8 @@ entry:
define i1 @test_NE_IssEbT(i16 %a, i16 %b) {
; CHECK-LABEL: test_NE_IssEbT:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sxth w8, w1
; CHECK-NEXT: cmn w8, w0, sxth
; CHECK-NEXT: sxth w8, w0
; CHECK-NEXT: cmn w8, w1, sxth
; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ret
entry:
Expand All @@ -370,8 +370,8 @@ entry:
define i1 @test_NE_IscEbT(i16 %a, i8 %b) {
; CHECK-LABEL: test_NE_IscEbT:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: and w8, w1, #0xff
; CHECK-NEXT: cmn w8, w0, sxth
; CHECK-NEXT: sxth w8, w0
; CHECK-NEXT: cmn w8, w1, uxtb
; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ret
entry:
Expand Down Expand Up @@ -412,8 +412,8 @@ entry:
define i1 @test_NE_IcsEbT(i8 %a, i16 %b) {
; CHECK-LABEL: test_NE_IcsEbT:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: sxth w8, w1
; CHECK-NEXT: cmn w8, w0, uxtb
; CHECK-NEXT: and w8, w0, #0xff
; CHECK-NEXT: cmn w8, w1, sxth
; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ret
entry:
Expand All @@ -427,8 +427,8 @@ entry:
define i1 @test_NE_IccEbT(i8 %a, i8 %b) {
; CHECK-LABEL: test_NE_IccEbT:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: and w8, w1, #0xff
; CHECK-NEXT: cmn w8, w0, uxtb
; CHECK-NEXT: and w8, w0, #0xff
; CHECK-NEXT: cmn w8, w1, uxtb
; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ret
entry:
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/AArch64/typepromotion-overflow.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -107,11 +107,11 @@ define i32 @overflow_add_const_limit(i8 zeroext %a, i8 zeroext %b) {
define i32 @overflow_add_positive_const_limit(i8 zeroext %a) {
; CHECK-LABEL: overflow_add_positive_const_limit:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #-1 // =0xffffffff
; CHECK-NEXT: mov w9, #8 // =0x8
; CHECK-NEXT: cmp w8, w0, sxtb
; CHECK-NEXT: sxtb w9, w0
; CHECK-NEXT: mov w8, #16 // =0x10
; CHECK-NEXT: csel w0, w9, w8, gt
; CHECK-NEXT: cmn w9, #1
; CHECK-NEXT: mov w9, #8 // =0x8
; CHECK-NEXT: csel w0, w9, w8, lt
; CHECK-NEXT: ret
%cmp = icmp slt i8 %a, -1
%res = select i1 %cmp, i32 8, i32 16
Expand Down Expand Up @@ -162,11 +162,11 @@ define i32 @safe_add_underflow_neg(i8 zeroext %a) {
define i32 @overflow_sub_negative_const_limit(i8 zeroext %a) {
; CHECK-LABEL: overflow_sub_negative_const_limit:
; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #-1 // =0xffffffff
; CHECK-NEXT: mov w9, #8 // =0x8
; CHECK-NEXT: cmp w8, w0, sxtb
; CHECK-NEXT: sxtb w9, w0
; CHECK-NEXT: mov w8, #16 // =0x10
; CHECK-NEXT: csel w0, w9, w8, gt
; CHECK-NEXT: cmn w9, #1
; CHECK-NEXT: mov w9, #8 // =0x8
; CHECK-NEXT: csel w0, w9, w8, lt
; CHECK-NEXT: ret
%cmp = icmp slt i8 %a, -1
%res = select i1 %cmp, i32 8, i32 16
Expand Down
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