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[SelectionDAG] Ensure that we don't create UCMP/SCMP nodes with operands being scalars and result being a 1-element vector during scalarization #98687

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Merged
merged 2 commits into from
Jul 12, 2024
Merged

[SelectionDAG] Ensure that we don't create UCMP/SCMP nodes with operands being scalars and result being a 1-element vector during scalarization #98687

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5c8cbec
[SelectionDAG] Correctly handle scalarization of UCMP/SCMP with legal…
Poseydon42 Jul 12, 2024
1abb56f
[SelectionDAG] Add assertions to verify validity of SCMP/UCMP node be…
Poseydon42 Jul 12, 2024
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5 changes: 4 additions & 1 deletion llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
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Expand Up @@ -1029,7 +1029,10 @@ SDValue DAGTypeLegalizer::ScalarizeVecOp_VECREDUCE_SEQ(SDNode *N) {
SDValue DAGTypeLegalizer::ScalarizeVecOp_CMP(SDNode *N) {
SDValue LHS = GetScalarizedVector(N->getOperand(0));
SDValue RHS = GetScalarizedVector(N->getOperand(1));
return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0), LHS, RHS);

EVT ResVT = N->getValueType(0).getVectorElementType();
SDValue Cmp = DAG.getNode(N->getOpcode(), SDLoc(N), ResVT, LHS, RHS);
return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(N), N->getValueType(0), Cmp);
}

//===----------------------------------------------------------------------===//
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11 changes: 11 additions & 0 deletions llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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Expand Up @@ -6983,6 +6983,17 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
return getNode(ISD::AND, DL, VT, N1, getNOT(DL, N2, VT));
}
break;
case ISD::SCMP:
case ISD::UCMP:
assert(N1.getValueType() == N2.getValueType() &&
"Types of operands of UCMP/SCMP must match");
assert(N1.getValueType().isVector() == VT.isVector() &&
"Operands and return type of must both be scalars or vectors");
if (VT.isVector())
assert(VT.getVectorElementCount() ==
N1.getValueType().getVectorElementCount() &&
"Result and operands must have the same number of elements");
break;
case ISD::AVGFLOORS:
case ISD::AVGFLOORU:
case ISD::AVGCEILS:
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17 changes: 17 additions & 0 deletions llvm/test/CodeGen/AArch64/ucmp.ll
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Expand Up @@ -93,3 +93,20 @@ define i64 @ucmp.64.64(i64 %x, i64 %y) nounwind {
%1 = call i64 @llvm.ucmp(i64 %x, i64 %y)
ret i64 %1
}

define <1 x i64> @ucmp.1.64.65(<1 x i65> %x, <1 x i65> %y) {
; CHECK-LABEL: ucmp.1.64.65:
; CHECK: // %bb.0:
; CHECK-NEXT: and x8, x1, #0x1
; CHECK-NEXT: and x9, x3, #0x1
; CHECK-NEXT: cmp x2, x0
; CHECK-NEXT: sbcs xzr, x9, x8
; CHECK-NEXT: cset x10, lo
; CHECK-NEXT: cmp x0, x2
; CHECK-NEXT: sbcs xzr, x8, x9
; CHECK-NEXT: csinv x8, x10, xzr, hs
; CHECK-NEXT: fmov d0, x8
; CHECK-NEXT: ret
%1 = call <1 x i64> @llvm.ucmp(<1 x i65> %x, <1 x i65> %y)
ret <1 x i64> %1
}
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