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[Target] Use range-based for loops (NFC) #98844

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Merged
merged 1 commit into from
Jul 16, 2024
Merged

[Target] Use range-based for loops (NFC) #98844

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4 changes: 2 additions & 2 deletions llvm/lib/Target/ARM/ARMConstantIslandPass.cpp
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Expand Up @@ -478,8 +478,8 @@ bool ARMConstantIslands::runOnMachineFunction(MachineFunction &mf) {

LLVM_DEBUG(dbgs() << "Beginning BR iteration #" << NoBRIters << '\n');
bool BRChange = false;
for (unsigned i = 0, e = ImmBranches.size(); i != e; ++i)
BRChange |= fixupImmediateBr(ImmBranches[i]);
for (ImmBranch &Br : ImmBranches)
BRChange |= fixupImmediateBr(Br);
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Looks like fixupImmediateBr resizes ImmBranches :)

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Thank you for letting me know. I've reverted the whole thing for now.

if (BRChange && ++NoBRIters > 30)
report_fatal_error("Branch Fix Up pass failed to converge!");
LLVM_DEBUG(dumpBBs());
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4 changes: 2 additions & 2 deletions llvm/lib/Target/ARM/ARMFrameLowering.cpp
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Expand Up @@ -1673,8 +1673,8 @@ void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
.addReg(ARM::SP)
.add(predOps(ARMCC::AL))
.setMIFlags(MachineInstr::FrameDestroy);
for (unsigned i = 0, e = Regs.size(); i < e; ++i)
MIB.addReg(Regs[i], getDefRegState(true));
for (unsigned Reg : Regs)
MIB.addReg(Reg, getDefRegState(true));
if (DeleteRet) {
if (MI != MBB.end()) {
MIB.copyImplicitOps(*MI);
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4 changes: 2 additions & 2 deletions llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
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Expand Up @@ -2579,8 +2579,8 @@ ARMPreAllocLoadStoreOpt::RescheduleLoadStoreInstrs(MachineBasicBlock *MBB) {
Bases.push_back(Base);
return;
}
for (unsigned i = 0, e = BI->second.size(); i != e; ++i) {
if (Offset == getMemoryOpOffset(*BI->second[i])) {
for (const MachineInstr *MI : BI->second) {
if (Offset == getMemoryOpOffset(*MI)) {
StopHere = true;
break;
}
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4 changes: 2 additions & 2 deletions llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
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Expand Up @@ -1056,8 +1056,8 @@ bool DeadCodeElimination::runOnNode(MachineDomTreeNode *N) {
continue;

B->erase(MI);
for (unsigned i = 0, n = Regs.size(); i != n; ++i)
MRI.markUsesInDebugValueAsUndef(Regs[i]);
for (unsigned Reg : Regs)
MRI.markUsesInDebugValueAsUndef(Reg);
Changed = true;
}

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12 changes: 6 additions & 6 deletions llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
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Expand Up @@ -1040,8 +1040,8 @@ void HexagonGenInsert::pruneEmptyLists() {
if (I->second.empty())
Prune.push_back(I);
}
for (unsigned i = 0, n = Prune.size(); i < n; ++i)
IFMap.erase(Prune[i]);
for (const auto &It : Prune)
IFMap.erase(It);
}

void HexagonGenInsert::pruneCoveredSets(unsigned VR) {
Expand Down Expand Up @@ -1470,8 +1470,8 @@ bool HexagonGenInsert::removeDeadCode(MachineDomTreeNode *N) {
continue;

B->erase(MI);
for (unsigned I = 0, N = Regs.size(); I != N; ++I)
MRI->markUsesInDebugValueAsUndef(Regs[I]);
for (unsigned Reg : Regs)
MRI->markUsesInDebugValueAsUndef(Reg);
Changed = true;
}

Expand Down Expand Up @@ -1582,8 +1582,8 @@ bool HexagonGenInsert::runOnMachineFunction(MachineFunction &MF) {
if (Idx >= Cutoff)
Out.push_back(I);
}
for (unsigned i = 0, n = Out.size(); i < n; ++i)
IFMap.erase(Out[i]);
for (const auto &It : Out)
IFMap.erase(It);
}
if (IFMap.empty())
return Changed;
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4 changes: 2 additions & 2 deletions llvm/lib/Target/Mips/MipsConstantIslandPass.cpp
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Expand Up @@ -500,8 +500,8 @@ bool MipsConstantIslands::runOnMachineFunction(MachineFunction &mf) {

LLVM_DEBUG(dbgs() << "Beginning BR iteration #" << NoBRIters << '\n');
bool BRChange = false;
for (unsigned i = 0, e = ImmBranches.size(); i != e; ++i)
BRChange |= fixupImmediateBr(ImmBranches[i]);
for (ImmBranch &Br : ImmBranches)
BRChange |= fixupImmediateBr(Br);
if (BRChange && ++NoBRIters > 30)
report_fatal_error("Branch Fix Up pass failed to converge!");
LLVM_DEBUG(dumpBBs());
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4 changes: 2 additions & 2 deletions llvm/lib/Target/Mips/MipsFastISel.cpp
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Expand Up @@ -1763,8 +1763,8 @@ bool MipsFastISel::selectRet(const Instruction *I) {
RetRegs.push_back(VA.getLocReg());
}
MachineInstrBuilder MIB = emitInst(Mips::RetRA);
for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
MIB.addReg(RetRegs[i], RegState::Implicit);
for (unsigned Reg : RetRegs)
MIB.addReg(Reg, RegState::Implicit);
return true;
}

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4 changes: 2 additions & 2 deletions llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
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Expand Up @@ -861,8 +861,8 @@ void NVPTXAsmPrinter::emitGlobals(const Module &M) {
*static_cast<const NVPTXSubtarget *>(NTM.getSubtargetImpl());

// Print out module-level global variables in proper order
for (unsigned i = 0, e = Globals.size(); i != e; ++i)
printModuleLevelGV(Globals[i], OS2, /*processDemoted=*/false, STI);
for (const GlobalVariable *GV : Globals)
printModuleLevelGV(GV, OS2, /*processDemoted=*/false, STI);

OS2 << '\n';

Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp
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Expand Up @@ -149,8 +149,8 @@ namespace {
Changed = true;
}

for (unsigned i = 0, ie = PredToRemove.size(); i != ie; ++i)
PredToRemove[i]->removeSuccessor(&ReturnMBB, true);
for (MachineBasicBlock *MBB : PredToRemove)
MBB->removeSuccessor(&ReturnMBB, true);

if (Changed && !ReturnMBB.hasAddressTaken()) {
// We now might be able to merge this blr-only block into its
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Target/PowerPC/PPCFastISel.cpp
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Expand Up @@ -1668,8 +1668,8 @@ bool PPCFastISel::fastLowerCall(CallLoweringInfo &CLI) {
}

// Add implicit physical register uses to the call.
for (unsigned II = 0, IE = RegArgs.size(); II != IE; ++II)
MIB.addReg(RegArgs[II], RegState::Implicit);
for (unsigned Reg : RegArgs)
MIB.addReg(Reg, RegState::Implicit);

// Direct calls, in both the ELF V1 and V2 ABIs, need the TOC register live
// into the call.
Expand Down Expand Up @@ -1793,8 +1793,8 @@ bool PPCFastISel::SelectRet(const Instruction *I) {
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(PPC::BLR8));

for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
MIB.addReg(RetRegs[i], RegState::Implicit);
for (unsigned Reg : RetRegs)
MIB.addReg(Reg, RegState::Implicit);

return true;
}
Expand Down
3 changes: 1 addition & 2 deletions llvm/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp
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Expand Up @@ -135,8 +135,7 @@ static void undefInvalidDbgValues(
#ifndef NDEBUG
DenseSet<Register> SeenRegs;
#endif
for (size_t I = 0, E = Assignments.size(); I < E; ++I) {
const auto &CoalescedIntervals = Assignments[I];
for (const auto &CoalescedIntervals : Assignments) {
if (CoalescedIntervals.empty())
continue;
for (LiveInterval *LI : CoalescedIntervals) {
Expand Down
5 changes: 2 additions & 3 deletions llvm/lib/Target/XCore/XCoreLowerThreadLocal.cpp
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Expand Up @@ -178,8 +178,7 @@ bool XCoreLowerThreadLocal::runOnModule(Module &M) {
for (GlobalVariable &GV : M.globals())
if (GV.isThreadLocal())
ThreadLocalGlobals.push_back(&GV);
for (unsigned I = 0, E = ThreadLocalGlobals.size(); I != E; ++I) {
MadeChange |= lowerGlobal(ThreadLocalGlobals[I]);
}
for (GlobalVariable *GV : ThreadLocalGlobals)
MadeChange |= lowerGlobal(GV);
return MadeChange;
}
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