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[AMDGPU][GlobaISel] wrap the load-splitting code in RegBank selection with condition #98966

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Merged
merged 2 commits into from
Jul 24, 2024
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[AMDGPU][GlobaISel] wrap the load-splitting code in RegBank selection with condition #98966

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95af891
[AMDGPU][GlobaISel] wrap the load-splitting code in RegBank selection
cmc-rep Jul 15, 2024
6f1d662
[AMDGPU] update the code based upon feedback
cmc-rep Jul 23, 2024
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32 changes: 18 additions & 14 deletions llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1059,6 +1059,7 @@ bool AMDGPURegisterBankInfo::applyMappingLoad(
Register DstReg = MI.getOperand(0).getReg();
const LLT LoadTy = MRI.getType(DstReg);
unsigned LoadSize = LoadTy.getSizeInBits();
MachineMemOperand *MMO = *MI.memoperands_begin();
const unsigned MaxNonSmrdLoadSize = 128;

const RegisterBank *DstBank =
Expand All @@ -1069,7 +1070,6 @@ bool AMDGPURegisterBankInfo::applyMappingLoad(
if (LoadSize != 32 && (LoadSize != 96 || Subtarget.hasScalarDwordx3Loads()))
return false;

MachineMemOperand *MMO = *MI.memoperands_begin();
const unsigned MemSize = 8 * MMO->getSize().getValue();
// Scalar loads of size 8 or 16 bit with proper alignment may be widened to
// 32 bit. Check to see if we need to widen the memory access, 8 or 16 bit
Expand Down Expand Up @@ -1142,25 +1142,29 @@ bool AMDGPURegisterBankInfo::applyMappingLoad(
if (SrcRegs.empty())
SrcRegs.push_back(MI.getOperand(1).getReg());

assert(LoadSize % MaxNonSmrdLoadSize == 0);

// RegBankSelect only emits scalar types, so we need to reset the pointer
// operand to a pointer type.
Register BasePtrReg = SrcRegs[0];
LLT PtrTy = MRI.getType(MI.getOperand(1).getReg());
MRI.setType(BasePtrReg, PtrTy);

unsigned NumSplitParts = LoadTy.getSizeInBits() / MaxNonSmrdLoadSize;
const LLT LoadSplitTy = LoadTy.divide(NumSplitParts);
ApplyRegBankMapping O(B, *this, MRI, &AMDGPU::VGPRRegBank);
LegalizerHelper Helper(B.getMF(), O, B);

if (LoadTy.isVector()) {
if (Helper.fewerElementsVector(MI, 0, LoadSplitTy) != LegalizerHelper::Legalized)
return false;
} else {
if (Helper.narrowScalar(MI, 0, LoadSplitTy) != LegalizerHelper::Legalized)
return false;
// The following are the loads not splitted enough during legalization
// because it was not clear they are smem-load or vmem-load
if (AMDGPU::isExtendedGlobalAddrSpace(MMO->getAddrSpace()) ||
MMO->getAddrSpace() == AMDGPUAS::BUFFER_RESOURCE) {
assert(LoadSize % MaxNonSmrdLoadSize == 0);
unsigned NumSplitParts = LoadTy.getSizeInBits() / MaxNonSmrdLoadSize;
const LLT LoadSplitTy = LoadTy.divide(NumSplitParts);
ApplyRegBankMapping O(B, *this, MRI, &AMDGPU::VGPRRegBank);
LegalizerHelper Helper(B.getMF(), O, B);
if (LoadTy.isVector()) {
if (Helper.fewerElementsVector(MI, 0, LoadSplitTy) !=
LegalizerHelper::Legalized)
return false;
} else {
if (Helper.narrowScalar(MI, 0, LoadSplitTy) != LegalizerHelper::Legalized)
return false;
}
}

MRI.setRegBank(DstReg, AMDGPU::VGPRRegBank);
Expand Down
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