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[InstCombine] Turn AShr into LShr more often in SimplifyDemandedUseBits #99155

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Merged
merged 1 commit into from
Jul 18, 2024
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[InstCombine] Turn AShr into LShr more often in SimplifyDemandedUseBits #99155

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26 changes: 11 additions & 15 deletions llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -806,34 +806,30 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Instruction *I,

// Signed shift right.
APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
// If any of the high bits are demanded, we should set the sign bit as
// demanded.
if (DemandedMask.countl_zero() <= ShiftAmt)
// If any of the bits being shifted in are demanded, then we should set
// the sign bit as demanded.
bool ShiftedInBitsDemanded = DemandedMask.countl_zero() < ShiftAmt;
if (ShiftedInBitsDemanded)
DemandedMaskIn.setSignBit();

if (SimplifyDemandedBits(I, 0, DemandedMaskIn, Known, Depth + 1, Q)) {
// exact flag may not longer hold.
I->dropPoisonGeneratingFlags();
return I;
}

Known = KnownBits::ashr(
Known, KnownBits::makeConstant(APInt(BitWidth, ShiftAmt)),
ShiftAmt != 0, I->isExact());

// If the input sign bit is known to be zero, or if none of the top bits
// are demanded, turn this into an unsigned shift right.
assert(BitWidth > ShiftAmt && "Shift amount not saturated?");
APInt HighBits(APInt::getHighBitsSet(
BitWidth, std::min(SignBits + ShiftAmt - 1, BitWidth)));
if (Known.Zero[BitWidth-ShiftAmt-1] ||
!DemandedMask.intersects(HighBits)) {
// If the input sign bit is known to be zero, or if none of the shifted in
// bits are demanded, turn this into an unsigned shift right.
if (Known.Zero[BitWidth - 1] || !ShiftedInBitsDemanded) {
BinaryOperator *LShr = BinaryOperator::CreateLShr(I->getOperand(0),
I->getOperand(1));
LShr->setIsExact(cast<BinaryOperator>(I)->isExact());
LShr->takeName(I);
return InsertNewInstWith(LShr, I->getIterator());
}

Known = KnownBits::ashr(
Known, KnownBits::makeConstant(APInt(BitWidth, ShiftAmt)),
ShiftAmt != 0, I->isExact());
} else {
llvm::computeKnownBits(I, Known, Depth, Q);
}
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9 changes: 3 additions & 6 deletions llvm/test/Transforms/InstCombine/ashr-demand.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -74,12 +74,9 @@ define i16 @ashr_can_be_lshr(i32 %a) {
; optimizations.
define i32 @ashr_can_be_lshr_2(i32 %a) {
; CHECK-LABEL: @ashr_can_be_lshr_2(
; CHECK-NEXT: [[TMP1:%.*]] = or i32 [[A:%.*]], 1056964608
; CHECK-NEXT: [[OR:%.*]] = zext i32 [[TMP1]] to i64
; CHECK-NEXT: [[SHL:%.*]] = shl i64 [[OR]], 34
; CHECK-NEXT: [[ASHR:%.*]] = ashr exact i64 [[SHL]], 32
; CHECK-NEXT: [[TRUNC:%.*]] = trunc nsw i64 [[ASHR]] to i32
; CHECK-NEXT: ret i32 [[TRUNC]]
; CHECK-NEXT: [[TMP1:%.*]] = shl i32 [[A:%.*]], 2
; CHECK-NEXT: [[TMP2:%.*]] = or i32 [[TMP1]], -67108864
; CHECK-NEXT: ret i32 [[TMP2]]
;
%ext = zext i32 %a to i64
%or = or i64 %ext, 4278190080
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