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[RISCV] Teach fillUpExtensionSupportForSplat to handle nxvXi64 VMV_V_X_VL on RV32. #99251

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Merged
merged 3 commits into from
Jul 17, 2024
Merged

[RISCV] Teach fillUpExtensionSupportForSplat to handle nxvXi64 VMV_V_X_VL on RV32. #99251

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b0ac7fa
[RISCV] Teach fillUpExtensionSupportForSplat to handle nxvXi64 VMV_V_…
topperc Jul 16, 2024
481c464
fixup! Fix comment
topperc Jul 17, 2024
716ec94
Merge remote-tracking branch 'origin/main' into HEAD
topperc Jul 17, 2024
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17 changes: 14 additions & 3 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -14503,10 +14503,21 @@ struct NodeExtensionHelper {
// widening opcode by splatting to smaller element size.
unsigned EltBits = VT.getScalarSizeInBits();
unsigned ScalarBits = Op.getValueSizeInBits();
// Make sure we're getting all element bits from the scalar register.
// FIXME: Support implicit sign extension of vmv.v.x?
if (ScalarBits < EltBits)
// If we're not getting all bits from the element, we need special handling.
if (ScalarBits < EltBits) {
// This should only occur on RV32.
assert(Opc == RISCVISD::VMV_V_X_VL && EltBits == 64 && ScalarBits == 32 &&
!Subtarget.is64Bit() && "Unexpected splat");
// vmv.v.x sign extends narrow inputs.
SupportsSExt = true;

// If the input is positive, then sign extend is also zero extend.
if (DAG.SignBitIsZero(Op))
SupportsZExt = true;

EnforceOneUse = false;
return;
}

unsigned NarrowSize = EltBits / 2;
// If the narrow type cannot be expressed with a legal VMV,
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