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[SelectionDAGBuilder][RISCV] Fix crash when using a memory constraint with scalable vector type. #99821

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merged 1 commit into from
Jul 22, 2024

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@topperc topperc commented Jul 21, 2024

We need to use the minimum size of the scalable type and the correct stack ID.

The code in the PR is still invalid because the instruction used doesn't have a pointer operand. This is diagnosed later when the assembler parses it.

Fixes #99782

… with scalable vector type.

We need to use the minimum size of the scalable type and the correct
stack ID.

The code in the PR is still invalid because the instruction used
doesn't have a pointer operand. This is diagnosed later when the
assembler parses it.
@llvmbot llvmbot added the llvm:SelectionDAG SelectionDAGISel as well label Jul 21, 2024
@topperc topperc changed the title [SelectionDAGBuilder][RISCV] Fix crash when using a memory constraint… [SelectionDAGBuilder][RISCV] Fix crash when using a memory constraint with scalable vector type. Jul 21, 2024
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llvmbot commented Jul 21, 2024

@llvm/pr-subscribers-llvm-selectiondag

Author: Craig Topper (topperc)

Changes

… with scalable vector type.

We need to use the minimum size of the scalable type and the correct stack ID.

The code in the PR is still invalid because the instruction used doesn't have a pointer operand. This is diagnosed later when the assembler parses it.


Full diff: https://github.com/llvm/llvm-project/pull/99821.diff

2 Files Affected:

  • (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (+8-3)
  • (added) llvm/test/CodeGen/RISCV/rvv/pr99782.ll (+18)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 98a795edb7a03..37b1131d2f8a3 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -9566,10 +9566,15 @@ static SDValue getAddressForMemoryInput(SDValue Chain, const SDLoc &Location,
   // Otherwise, create a stack slot and emit a store to it before the asm.
   Type *Ty = OpVal->getType();
   auto &DL = DAG.getDataLayout();
-  uint64_t TySize = DL.getTypeAllocSize(Ty);
+  TypeSize TySize = DL.getTypeAllocSize(Ty);
   MachineFunction &MF = DAG.getMachineFunction();
-  int SSFI = MF.getFrameInfo().CreateStackObject(
-      TySize, DL.getPrefTypeAlign(Ty), false);
+  const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
+  int StackID = 0;
+  if (TySize.isScalable())
+    StackID = TFI->getStackIDForScalableVectors();
+  int SSFI = MF.getFrameInfo().CreateStackObject(TySize.getKnownMinValue(),
+                                                 DL.getPrefTypeAlign(Ty), false,
+                                                 nullptr, StackID);
   SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getFrameIndexTy(DL));
   Chain = DAG.getTruncStore(Chain, Location, OpInfo.CallOperand, StackSlot,
                             MachinePointerInfo::getFixedStack(MF, SSFI),
diff --git a/llvm/test/CodeGen/RISCV/rvv/pr99782.ll b/llvm/test/CodeGen/RISCV/rvv/pr99782.ll
new file mode 100644
index 0000000000000..92c40f41f02b5
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rvv/pr99782.ll
@@ -0,0 +1,18 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=riscv64 -mattr=+v -stop-after=finalize-isel | FileCheck %s
+
+define void @vslidedown() {
+  ; CHECK-LABEL: name: vslidedown
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0.v, 0
+  ; CHECK-NEXT:   [[VL8RE8_V:%[0-9]+]]:vrm8 = VL8RE8_V killed [[ADDI]] :: (load (<vscale x 1 x s512>) from %ir.v, align 1)
+  ; CHECK-NEXT:   [[ADDI1:%[0-9]+]]:gpr = ADDI %stack.1, 0
+  ; CHECK-NEXT:   VS8R_V killed [[VL8RE8_V]], killed [[ADDI1]] :: (store (<vscale x 1 x s512>) into %stack.1)
+  ; CHECK-NEXT:   INLINEASM &"vadd.vv $0, $0, $0", 25 /* sideeffect mayload maystore attdialect */, 262166 /* mem:m */, %stack.0.v, 0, 262166 /* mem:m */, %stack.1, 0
+  ; CHECK-NEXT:   PseudoRET
+entry:
+  %v = alloca <vscale x 64 x i8>, align 1
+  %0 = load <vscale x 64 x i8>, ptr %v, align 1
+  call void asm sideeffect "vadd.vv $0, $0, $0", "=*imr,imr"(ptr elementtype(<vscale x 64 x i8>) %v, <vscale x 64 x i8> %0)
+  ret void
+}

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LGTM

@topperc topperc merged commit 1c798e0 into llvm:main Jul 22, 2024
9 checks passed
@topperc topperc deleted the pr/inline-asm-crash branch July 22, 2024 16:42
lukel97 added a commit that referenced this pull request Jul 24, 2024
yuxuanchen1997 pushed a commit that referenced this pull request Jul 25, 2024
… with scalable vector type. (#99821)

Summary:
We need to use the minimum size of the scalable type and the correct
stack ID.

The code in the PR is still invalid because the instruction used doesn't
have a pointer operand. This is diagnosed later when the assembler
parses it.

Fixes #99782

Test Plan: 

Reviewers: 

Subscribers: 

Tasks: 

Tags: 


Differential Revision: https://phabricator.intern.facebook.com/D60251084
yuxuanchen1997 pushed a commit that referenced this pull request Jul 25, 2024
Summary: 

Test Plan: 

Reviewers: 

Subscribers: 

Tasks: 

Tags: 


Differential Revision: https://phabricator.intern.facebook.com/D60250730
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[RISC-V][RVV] Inline ASM causes 'Invalid size request on a scalable vector'
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