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[RISCV] Copy call frame size when splitting basic block in emitSelectPseudo. #99823

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merged 1 commit into from
Jul 22, 2024

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topperc
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@topperc topperc commented Jul 21, 2024

Fixes #97304.

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llvmbot commented Jul 21, 2024

@llvm/pr-subscribers-backend-risc-v

Author: Craig Topper (topperc)

Changes

Fixes #97304.


Full diff: https://github.com/llvm/llvm-project/pull/99823.diff

2 Files Affected:

  • (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+5)
  • (added) llvm/test/CodeGen/RISCV/pr97304.ll (+51)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index e938454b8e642..585d8a060fe94 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -18478,6 +18478,11 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI,
   F->insert(I, IfFalseMBB);
   F->insert(I, TailMBB);
 
+  // Set the call frame size on entry to the new basic blocks.
+  unsigned CallFrameSize = TII.getCallFrameSizeAt(MI);
+  IfFalseMBB->setCallFrameSize(CallFrameSize);
+  TailMBB->setCallFrameSize(CallFrameSize);
+
   // Transfer debug instructions associated with the selects to TailMBB.
   for (MachineInstr *DebugInstr : SelectDebugValues) {
     TailMBB->push_back(DebugInstr->removeFromParent());
diff --git a/llvm/test/CodeGen/RISCV/pr97304.ll b/llvm/test/CodeGen/RISCV/pr97304.ll
new file mode 100644
index 0000000000000..120a0e787384d
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/pr97304.ll
@@ -0,0 +1,51 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=riscv64 -verify-machineinstrs -stop-after=finalize-isel | FileCheck %s
+
+define i32 @_ZNK2cv12LMSolverImpl3runERKNS_17_InputOutputArrayE(i1 %cmp436) {
+  ; CHECK-LABEL: name: _ZNK2cv12LMSolverImpl3runERKNS_17_InputOutputArrayE
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT:   liveins: $x10
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x10
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY [[COPY]]
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.for.cond:
+  ; CHECK-NEXT:   successors: %bb.2(0x40000000), %bb.3(0x40000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY1]], 1
+  ; CHECK-NEXT:   ADJCALLSTACKDOWN 8, 0, implicit-def dead $x2, implicit $x2
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $x2
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gprjalr = COPY $x0
+  ; CHECK-NEXT:   SD [[COPY3]], [[COPY2]], 0 :: (store (s64))
+  ; CHECK-NEXT:   [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 1
+  ; CHECK-NEXT:   [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 32
+  ; CHECK-NEXT:   BNE [[ANDI]], $x0, %bb.3
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.for.cond (call-frame-size 8):
+  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.3.for.cond (call-frame-size 8):
+  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gpr = PHI [[ADDI1]], %bb.1, [[ADDI]], %bb.2
+  ; CHECK-NEXT:   $x10 = COPY [[COPY3]]
+  ; CHECK-NEXT:   $x11 = COPY [[PHI]]
+  ; CHECK-NEXT:   $x12 = COPY [[COPY3]]
+  ; CHECK-NEXT:   $x13 = COPY [[COPY3]]
+  ; CHECK-NEXT:   $x14 = COPY [[COPY3]]
+  ; CHECK-NEXT:   $x15 = COPY [[COPY3]]
+  ; CHECK-NEXT:   $x16 = COPY [[COPY3]]
+  ; CHECK-NEXT:   $x17 = COPY [[COPY3]]
+  ; CHECK-NEXT:   PseudoCALLIndirect [[COPY3]], csr_ilp32_lp64, implicit-def dead $x1, implicit $x10, implicit $x11, implicit $x12, implicit $x13, implicit $x14, implicit $x15, implicit $x16, implicit $x17, implicit-def $x2, implicit-def $x10
+  ; CHECK-NEXT:   ADJCALLSTACKUP 8, 0, implicit-def dead $x2, implicit $x2
+  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:gpr = COPY $x10
+  ; CHECK-NEXT:   PseudoBR %bb.1
+entry:
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.cond, %entry
+  %conv = select i1 %cmp436, i32 32, i32 1
+  %call479 = call i32 (ptr, ...) null(ptr null, i32 %conv, i32 0, i32 0, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00, double 0.000000e+00)
+  br label %for.cond
+}

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LGTM

I'll note the underlying scheme seems very fragile. This may not be the only case like this we need to identify.

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preames commented Jul 22, 2024

I'll note the underlying scheme seems very fragile. This may not be the only case like this we need to identify.

We have several other places in the same file where we manually create MI control flow. Don't we need to update every one of those?

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asb commented Jul 22, 2024

I'll note the underlying scheme seems very fragile. This may not be the only case like this we need to identify.

We have several other places in the same file where we manually create MI control flow. Don't we need to update every one of those?

I'm also wondering this - is there any reference on when this is necessary?

Broader questions aside, change LGTM.

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topperc commented Jul 22, 2024

I'll note the underlying scheme seems very fragile. This may not be the only case like this we need to identify.

We have several other places in the same file where we manually create MI control flow. Don't we need to update every one of those?

Yes we do. I'll try to work on tests for the other places.

@topperc topperc merged commit 2c92335 into llvm:main Jul 22, 2024
9 checks passed
@topperc topperc deleted the pr/97304 branch July 22, 2024 16:21
yuxuanchen1997 pushed a commit that referenced this pull request Jul 25, 2024
…Pseudo. (#99823)

Summary: Fixes #97304.

Test Plan: 

Reviewers: 

Subscribers: 

Tasks: 

Tags: 


Differential Revision: https://phabricator.intern.facebook.com/D60251289
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[RISCV] Call frame size on entry does not match assertion with -verify-machineinstrs
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