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[GISEL][RISCV] RegBank Scalable Vector Load/Store #99932

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Merged
merged 8 commits into from
Jul 31, 2024
Merged

[GISEL][RISCV] RegBank Scalable Vector Load/Store #99932

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75d36b9
register bank select for scalable vector load/store
jiahanxie353 Jul 22, 2024
a700261
made some changes based on review
jiahanxie353 Jul 30, 2024
382cbd7
use type size instead of unsigned when getting value mapping
jiahanxie353 Jul 30, 2024
6f2b1ae
OpsMapping[1] is always GPR; use getFixedValue when type is not vector
jiahanxie353 Jul 30, 2024
7683e28
use getFixedValue() from size directly
jiahanxie353 Jul 30, 2024
c04c4ec
correct testing code
jiahanxie353 Jul 31, 2024
93fcb52
early break if Ty isVector
jiahanxie353 Jul 31, 2024
2fe4c15
update test files (previously using the result of regbankselect direc…
jiahanxie353 Jul 31, 2024
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5 changes: 3 additions & 2 deletions llvm/lib/CodeGen/RegisterBankInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -215,8 +215,9 @@ RegisterBankInfo::getInstrMappingImpl(const MachineInstr &MI) const {
}
}

unsigned Size = getSizeInBits(Reg, MRI, TRI);
const ValueMapping *ValMapping = &getValueMapping(0, Size, *CurRegBank);
TypeSize Size = getSizeInBits(Reg, MRI, TRI);
const ValueMapping *ValMapping =
&getValueMapping(0, Size.getKnownMinValue(), *CurRegBank);
if (IsCopyLike) {
if (!OperandsMapping[0]) {
if (MI.isRegSequence()) {
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25 changes: 21 additions & 4 deletions llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -310,10 +310,18 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
switch (Opc) {
case TargetOpcode::G_LOAD: {
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
OpdsMapping[0] = GPRValueMapping;
TypeSize Size = Ty.getSizeInBits();
if (Ty.isVector())
OpdsMapping[0] = getVRBValueMapping(Size.getKnownMinValue());
else
OpdsMapping[0] = GPRValueMapping;

OpdsMapping[1] = GPRValueMapping;

if (Ty.isVector())
break;
// Use FPR64 for s64 loads on rv32.
if (GPRSize == 32 && Ty.getSizeInBits() == 64) {
if (GPRSize == 32 && Size.getFixedValue() == 64) {
assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
break;
Expand All @@ -333,10 +341,19 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
}
case TargetOpcode::G_STORE: {
LLT Ty = MRI.getType(MI.getOperand(0).getReg());
OpdsMapping[0] = GPRValueMapping;
TypeSize Size = Ty.getSizeInBits();
if (Ty.isVector())
OpdsMapping[0] = getVRBValueMapping(Size.getKnownMinValue());
else
OpdsMapping[0] = GPRValueMapping;

OpdsMapping[1] = GPRValueMapping;

if (Ty.isVector())
break;

// Use FPR64 for s64 stores on rv32.
if (GPRSize == 32 && Ty.getSizeInBits() == 64) {
if (GPRSize == 32 && Size.getFixedValue() == 64) {
assert(MF.getSubtarget<RISCVSubtarget>().hasStdExtD());
OpdsMapping[0] = getFPValueMapping(Ty.getSizeInBits());
break;
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