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STM32F7 QSPI flash timeouts and 4-byte addressing #152

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Mar 21, 2023
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Original file line number Diff line number Diff line change
Expand Up @@ -1095,7 +1095,6 @@ int QSPIFBlockDevice::_handle_vendor_quirks()
_needs_fast_mode = true;
_num_status_registers = 3;
_read_status_reg_2_inst = QSPIF_INST_RDCR;
_attempt_4_byte_addressing = false;
break;
case 0x9d:
// ISSI devices have only one status register
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Original file line number Diff line number Diff line change
Expand Up @@ -571,10 +571,8 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
__HAL_DMA_DISABLE(hqspi->hdma);
}

#if defined(QSPI1_V1_0)
/* Clear Busy bit */
HAL_QSPI_Abort_IT(hqspi);
#endif

/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
Expand Down Expand Up @@ -616,10 +614,8 @@ void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
}
}

#if defined(QSPI1_V1_0)
/* Workaround - Extra data written in the FIFO at the end of a read transfer */
HAL_QSPI_Abort_IT(hqspi);
#endif

/* Change state of QSPI */
hqspi->State = HAL_QSPI_STATE_READY;
Expand Down Expand Up @@ -1021,10 +1017,8 @@ HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, u
/* Clear Transfer Complete bit */
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);

#if defined(QSPI1_V1_0)
/* Clear Busy bit */
status = HAL_QSPI_Abort(hqspi);
#endif
}
}

Expand Down Expand Up @@ -1112,10 +1106,8 @@ HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, ui
/* Clear Transfer Complete bit */
__HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);

#if defined(QSPI1_V1_0)
/* Workaround - Extra data written in the FIFO at the end of a read transfer */
status = HAL_QSPI_Abort(hqspi);
#endif
}
}

Expand Down