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DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/compute_units/CMakeLists.txt
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set(CMAKE_CXX_COMPILER "dpcpp") | ||
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cmake_minimum_required (VERSION 2.8) | ||
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project(ComputeUnits) | ||
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set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) | ||
set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) | ||
set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}) | ||
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add_subdirectory (src) |
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DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/compute_units/License.txt
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Copyright Intel Corporation | ||
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Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: | ||
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The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. | ||
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/compute_units/README.md
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# Using Compute Units To Duplicate Kernels | ||
This FPGA tutorial showcases a design pattern that allows you to make multiple copies of a kernel, called compute units. | ||
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***Documentation***: The [oneAPI DPC++ FPGA Optimization Guide](https://software.intel.com/content/www/us/en/develop/documentation/oneapi-fpga-optimization-guide) provides comprehensive instructions for targeting FPGAs through DPC++. The [oneAPI Programming Guide](https://software.intel.com/en-us/oneapi-programming-guide) is a general resource for target-independent DPC++ programming. | ||
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| Optimized for | Description | ||
--- |--- | ||
| OS | Linux* Ubuntu* 18.04; Windows* 10 | ||
| Hardware | Intel® Programmable Acceleration Card (PAC) with Intel Arria® 10 GX FPGA; <br> Intel® Programmable Acceleration Card (PAC) with Intel Stratix® 10 SX FPGA | ||
| Software | Intel® oneAPI DPC++ Compiler (Beta) <br> Intel® FPGA Add-On for oneAPI Base Toolkit | ||
| What you will learn | A design pattern to generate multiple compute units in DPC++ using template metaprogramming | ||
| Time to complete | 15 minutes | ||
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_Notice: Limited support in Windows*; compiling for FPGA hardware is not supported in Windows*_ | ||
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## Purpose | ||
The performance of a design can sometimes by increased by making multiple copies of kernels, to make full use of the FPGA resources. Each kernel copy is called a compute unit. | ||
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This tutorial provides a header file that defines an abstraction for making multiple copies of a single-task kernel. This header can be used in any DPC++ design and can be extended as necessary. | ||
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### Compute units example | ||
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This code sample builds on the pipe_array tutorial. It includes the header files `pipe_array.hpp`, `pipe_array_internal.hpp`, and `unroller.hpp` from the pipe_array tutorial, and provides the `compute_units.hpp` header as well. | ||
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This code sample defines a `Source` kernel, and a `Sink` kernel. Data is read from host memory by the `Source` kernel, and sent to the `Sink` kernel via a chain of compute units. The number of compute units in the chain between `Source` and `Sink` is determined by the following parameter: | ||
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``` c++ | ||
constexpr size_t kEngines = 5; | ||
``` | ||
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Data is passed between kernels using pipes. The number of pipes needed is equal to the length of the chain, i.e., the number of compute units, plus one. | ||
This array of pipes is declared as follows: | ||
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``` c++ | ||
using Pipes = PipeArray<class MyPipe, float, 1, kEngines + 1>; | ||
``` | ||
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The `Source` kernel reads data from host memory and writes it to the first pipe: | ||
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``` c++ | ||
void SourceKernel(queue &q, float data) { | ||
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q.submit([&](handler &h) { | ||
h.single_task<Source>([=] { Pipes::PipeAt<0>::write(data); }); | ||
}); | ||
} | ||
``` | ||
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At the end of the chain, the `Sink` kernel reads data from the last pipe and returns it to the host: | ||
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``` c++ | ||
void SinkKernel(queue &q, float *out_data) { | ||
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// The verbose buffer syntax is necessary here, | ||
// since out_data is just a single scalar value | ||
// and its size can not be inferred automatically | ||
buffer<float, 1> out_buf(out_data, 1); | ||
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q.submit([&](handler &h) { | ||
auto out_accessor = out_buf.get_access<access::mode::write>(h); | ||
h.single_task<Sink>( | ||
[=] { out_accessor[0] = Pipes::PipeAt<kEngines>::read(); }); | ||
}); | ||
} | ||
``` | ||
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The following line defines the functionality of each compute unit, and submits each compute unit to the given queue `q`. The number of copies to submit is provided by the first template parameter of `submit_compute_units`, while the second template parameter allows you to give the compute units a shared base name, e.g., `ChainComputeUnit`. The functionality of each compute unit must be specified by a generic lambda expression, that takes a single argument (with type `auto`) that provides an ID for each compute unit: | ||
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``` c++ | ||
intelfpga::submit_compute_units<kEngines, ChainComputeUnit>(q, [=](auto ID) { | ||
auto f = Pipes::PipeAt<ID>::read(); | ||
Pipes::PipeAt<ID + 1>::write(f); | ||
}); | ||
``` | ||
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Each compute unit in the chain from `Source` to `Sink` must read from a unique pipe, and write to the next pipe. As seen above, each compute unit knows its own ID and therefore its behavior can depend on this ID. Each compute unit in the chain will read from pipe `ID` and write to pipe `ID + 1`. | ||
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## Key Concepts | ||
* A design pattern to generate multiple compute units in DPC++ using template metaprogramming | ||
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## License | ||
This code sample is licensed under MIT license. | ||
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## Building the `compute_units` Tutorial | ||
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### Include Files | ||
The included header `dpc_common.hpp` is located at `%ONEAPI_ROOT%\dev-utilities\latest\include` on your development system. | ||
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### Running Samples in DevCloud | ||
If running a sample in the Intel DevCloud, remember that you must specify the compute node (fpga_compile or fpga_runtime) as well as whether to run in batch or interactive mode. For more information see the Intel® oneAPI Base Toolkit Get Started Guide ([https://devcloud.intel.com/oneapi/get-started/base-toolkit/](https://devcloud.intel.com/oneapi/get-started/base-toolkit/)). | ||
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When compiling for FPGA hardware, it is recommended to increase the job timeout to 12h. | ||
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### On a Linux* System | ||
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1. Generate the `Makefile` by running `cmake`. | ||
``` | ||
mkdir build | ||
cd build | ||
``` | ||
To compile for the Intel® PAC with Intel Arria® 10 GX FPGA, run `cmake` using the command: | ||
``` | ||
cmake .. | ||
``` | ||
Alternatively, to compile for the Intel® PAC with Intel Stratix® 10 SX FPGA, run `cmake` using the command: | ||
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``` | ||
cmake .. -DFPGA_BOARD=intel_s10sx_pac:pac_s10 | ||
``` | ||
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2. Compile the design through the generated `Makefile`. The following build targets are provided, matching the recommended development flow: | ||
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* Compile for emulation (fast compile time, targets emulated FPGA device): | ||
``` | ||
make fpga_emu | ||
``` | ||
* Generate the optimization report: | ||
``` | ||
make report | ||
``` | ||
* Compile for FPGA hardware (longer compile time, targets FPGA device): | ||
``` | ||
make fpga | ||
``` | ||
3. (Optional) As the above hardware compile may take several hours to complete, an Intel® PAC with Intel Arria® 10 GX FPGA precompiled binary can be downloaded <a href="https://software.intel.com/content/dam/develop/external/us/en/documents/compute_units.fpga.tar.gz" download>here</a>. | ||
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### In Third-Party Integrated Development Environments (IDEs) | ||
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You can compile and run this tutorial in the Eclipse* IDE (in Linux*). For instructions, refer to the following link: [Intel® oneAPI DPC++ FPGA Workflows on Third-Party IDEs](https://software.intel.com/en-us/articles/intel-oneapi-dpcpp-fpga-workflow-on-ide) | ||
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## Examining the Reports | ||
Locate `report.html` in the `compute_units_report.prj/reports/` or `compute_units_s10_pac_report.prj/reports/` directory. Open the report in any of Chrome*, Firefox*, Edge*, or Internet Explorer*. | ||
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You can visualize the kernels and pipes generated by looking at the "System Viewer" section of the report. Note that each compute unit is shown as a unique kernel in the reports, with names `ChainComputeUnit<0>`, `ChainComputeUnit<1>`, etc. | ||
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## Running the Sample | ||
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1. Run the sample on the FPGA emulator (the kernels execute on the CPU): | ||
``` | ||
./compute_units.fpga_emu (Linux) | ||
compute_units.fpga_emu.exe (Windows) | ||
``` | ||
2. Run the sample on the FPGA device: | ||
``` | ||
./compute_units.fpga (Linux) | ||
``` | ||
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### Example of Output | ||
``` | ||
PASSED: The results are correct | ||
``` |
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DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/compute_units/compute_units.sln
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DirectProgramming/DPC++FPGA/Tutorials/DesignPatterns/compute_units/compute_units.vcxproj
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