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net: hns3: Add enable and process hw errors of TM scheduler
This patch enables and process hw errors of TM scheduler and QCN(Quantized Congestion Control). Signed-off-by: Shiju Jose <[email protected]> Signed-off-by: Salil Mehta <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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‎drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -211,13 +211,21 @@ enum hclge_opcode_type {
211211
HCLGE_OPC_LED_STATUS_CFG = 0xB000,
212212

213213
/* Error INT commands */
214+
HCLGE_TM_SCH_ECC_INT_EN = 0x0829,
215+
HCLGE_TM_SCH_ECC_ERR_RINT_CMD = 0x082d,
216+
HCLGE_TM_SCH_ECC_ERR_RINT_CE = 0x082f,
217+
HCLGE_TM_SCH_ECC_ERR_RINT_NFE = 0x0830,
218+
HCLGE_TM_SCH_ECC_ERR_RINT_FE = 0x0831,
219+
HCLGE_TM_SCH_MBIT_ECC_INFO_CMD = 0x0833,
214220
HCLGE_COMMON_ECC_INT_CFG = 0x1505,
215221
HCLGE_IGU_EGU_TNL_INT_QUERY = 0x1802,
216222
HCLGE_IGU_EGU_TNL_INT_EN = 0x1803,
217223
HCLGE_IGU_EGU_TNL_INT_CLR = 0x1804,
218224
HCLGE_IGU_COMMON_INT_QUERY = 0x1805,
219225
HCLGE_IGU_COMMON_INT_EN = 0x1806,
220226
HCLGE_IGU_COMMON_INT_CLR = 0x1807,
227+
HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14,
228+
HCLGE_TM_QCN_MEM_INT_INFO_CMD = 0x1A17,
221229
HCLGE_PPP_CMD0_INT_CMD = 0x2100,
222230
HCLGE_PPP_CMD1_INT_CMD = 0x2101,
223231
HCLGE_NCSI_INT_QUERY = 0x2400,

‎drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

Lines changed: 286 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -213,6 +213,129 @@ static const struct hclge_hw_error hclge_ppp_mpf_int3[] = {
213213
{ /* sentinel */ }
214214
};
215215

216+
struct hclge_tm_sch_ecc_info {
217+
const char *name;
218+
};
219+
220+
static const struct hclge_tm_sch_ecc_info hclge_tm_sch_ecc_err[7][15] = {
221+
{
222+
{ .name = "QSET_QUEUE_CTRL:PRI_LEN TAB" },
223+
{ .name = "QSET_QUEUE_CTRL:SPA_LEN TAB" },
224+
{ .name = "QSET_QUEUE_CTRL:SPB_LEN TAB" },
225+
{ .name = "QSET_QUEUE_CTRL:WRRA_LEN TAB" },
226+
{ .name = "QSET_QUEUE_CTRL:WRRB_LEN TAB" },
227+
{ .name = "QSET_QUEUE_CTRL:SPA_HPTR TAB" },
228+
{ .name = "QSET_QUEUE_CTRL:SPB_HPTR TAB" },
229+
{ .name = "QSET_QUEUE_CTRL:WRRA_HPTR TAB" },
230+
{ .name = "QSET_QUEUE_CTRL:WRRB_HPTR TAB" },
231+
{ .name = "QSET_QUEUE_CTRL:QS_LINKLIST TAB" },
232+
{ .name = "QSET_QUEUE_CTRL:SPA_TPTR TAB" },
233+
{ .name = "QSET_QUEUE_CTRL:SPB_TPTR TAB" },
234+
{ .name = "QSET_QUEUE_CTRL:WRRA_TPTR TAB" },
235+
{ .name = "QSET_QUEUE_CTRL:WRRB_TPTR TAB" },
236+
{ .name = "QSET_QUEUE_CTRL:QS_DEFICITCNT TAB" },
237+
},
238+
{
239+
{ .name = "ROCE_QUEUE_CTRL:QS_LEN TAB" },
240+
{ .name = "ROCE_QUEUE_CTRL:QS_TPTR TAB" },
241+
{ .name = "ROCE_QUEUE_CTRL:QS_HPTR TAB" },
242+
{ .name = "ROCE_QUEUE_CTRL:QLINKLIST TAB" },
243+
{ .name = "ROCE_QUEUE_CTRL:QCLEN TAB" },
244+
},
245+
{
246+
{ .name = "NIC_QUEUE_CTRL:QS_LEN TAB" },
247+
{ .name = "NIC_QUEUE_CTRL:QS_TPTR TAB" },
248+
{ .name = "NIC_QUEUE_CTRL:QS_HPTR TAB" },
249+
{ .name = "NIC_QUEUE_CTRL:QLINKLIST TAB" },
250+
{ .name = "NIC_QUEUE_CTRL:QCLEN TAB" },
251+
},
252+
{
253+
{ .name = "RAM_CFG_CTRL:CSHAP TAB" },
254+
{ .name = "RAM_CFG_CTRL:PSHAP TAB" },
255+
},
256+
{
257+
{ .name = "SHAPER_CTRL:PSHAP TAB" },
258+
},
259+
{
260+
{ .name = "MSCH_CTRL" },
261+
},
262+
{
263+
{ .name = "TOP_CTRL" },
264+
},
265+
};
266+
267+
static const struct hclge_hw_error hclge_tm_sch_err_int[] = {
268+
{ .int_msk = BIT(0), .msg = "tm_sch_ecc_1bit_err" },
269+
{ .int_msk = BIT(1), .msg = "tm_sch_ecc_mbit_err" },
270+
{ .int_msk = BIT(2), .msg = "tm_sch_port_shap_sub_fifo_wr_full_err" },
271+
{ .int_msk = BIT(3), .msg = "tm_sch_port_shap_sub_fifo_rd_empty_err" },
272+
{ .int_msk = BIT(4), .msg = "tm_sch_pg_pshap_sub_fifo_wr_full_err" },
273+
{ .int_msk = BIT(5), .msg = "tm_sch_pg_pshap_sub_fifo_rd_empty_err" },
274+
{ .int_msk = BIT(6), .msg = "tm_sch_pg_cshap_sub_fifo_wr_full_err" },
275+
{ .int_msk = BIT(7), .msg = "tm_sch_pg_cshap_sub_fifo_rd_empty_err" },
276+
{ .int_msk = BIT(8), .msg = "tm_sch_pri_pshap_sub_fifo_wr_full_err" },
277+
{ .int_msk = BIT(9), .msg = "tm_sch_pri_pshap_sub_fifo_rd_empty_err" },
278+
{ .int_msk = BIT(10), .msg = "tm_sch_pri_cshap_sub_fifo_wr_full_err" },
279+
{ .int_msk = BIT(11), .msg = "tm_sch_pri_cshap_sub_fifo_rd_empty_err" },
280+
{ .int_msk = BIT(12),
281+
.msg = "tm_sch_port_shap_offset_fifo_wr_full_err" },
282+
{ .int_msk = BIT(13),
283+
.msg = "tm_sch_port_shap_offset_fifo_rd_empty_err" },
284+
{ .int_msk = BIT(14),
285+
.msg = "tm_sch_pg_pshap_offset_fifo_wr_full_err" },
286+
{ .int_msk = BIT(15),
287+
.msg = "tm_sch_pg_pshap_offset_fifo_rd_empty_err" },
288+
{ .int_msk = BIT(16),
289+
.msg = "tm_sch_pg_cshap_offset_fifo_wr_full_err" },
290+
{ .int_msk = BIT(17),
291+
.msg = "tm_sch_pg_cshap_offset_fifo_rd_empty_err" },
292+
{ .int_msk = BIT(18),
293+
.msg = "tm_sch_pri_pshap_offset_fifo_wr_full_err" },
294+
{ .int_msk = BIT(19),
295+
.msg = "tm_sch_pri_pshap_offset_fifo_rd_empty_err" },
296+
{ .int_msk = BIT(20),
297+
.msg = "tm_sch_pri_cshap_offset_fifo_wr_full_err" },
298+
{ .int_msk = BIT(21),
299+
.msg = "tm_sch_pri_cshap_offset_fifo_rd_empty_err" },
300+
{ .int_msk = BIT(22), .msg = "tm_sch_rq_fifo_wr_full_err" },
301+
{ .int_msk = BIT(23), .msg = "tm_sch_rq_fifo_rd_empty_err" },
302+
{ .int_msk = BIT(24), .msg = "tm_sch_nq_fifo_wr_full_err" },
303+
{ .int_msk = BIT(25), .msg = "tm_sch_nq_fifo_rd_empty_err" },
304+
{ .int_msk = BIT(26), .msg = "tm_sch_roce_up_fifo_wr_full_err" },
305+
{ .int_msk = BIT(27), .msg = "tm_sch_roce_up_fifo_rd_empty_err" },
306+
{ .int_msk = BIT(28), .msg = "tm_sch_rcb_byte_fifo_wr_full_err" },
307+
{ .int_msk = BIT(29), .msg = "tm_sch_rcb_byte_fifo_rd_empty_err" },
308+
{ .int_msk = BIT(30), .msg = "tm_sch_ssu_byte_fifo_wr_full_err" },
309+
{ .int_msk = BIT(31), .msg = "tm_sch_ssu_byte_fifo_rd_empty_err" },
310+
{ /* sentinel */ }
311+
};
312+
313+
static const struct hclge_hw_error hclge_qcn_ecc_err_int[] = {
314+
{ .int_msk = BIT(0), .msg = "qcn_byte_mem_ecc_1bit_err" },
315+
{ .int_msk = BIT(1), .msg = "qcn_byte_mem_ecc_mbit_err" },
316+
{ .int_msk = BIT(2), .msg = "qcn_time_mem_ecc_1bit_err" },
317+
{ .int_msk = BIT(3), .msg = "qcn_time_mem_ecc_mbit_err" },
318+
{ .int_msk = BIT(4), .msg = "qcn_fb_mem_ecc_1bit_err" },
319+
{ .int_msk = BIT(5), .msg = "qcn_fb_mem_ecc_mbit_err" },
320+
{ .int_msk = BIT(6), .msg = "qcn_link_mem_ecc_1bit_err" },
321+
{ .int_msk = BIT(7), .msg = "qcn_link_mem_ecc_mbit_err" },
322+
{ .int_msk = BIT(8), .msg = "qcn_rate_mem_ecc_1bit_err" },
323+
{ .int_msk = BIT(9), .msg = "qcn_rate_mem_ecc_mbit_err" },
324+
{ .int_msk = BIT(10), .msg = "qcn_tmplt_mem_ecc_1bit_err" },
325+
{ .int_msk = BIT(11), .msg = "qcn_tmplt_mem_ecc_mbit_err" },
326+
{ .int_msk = BIT(12), .msg = "qcn_shap_cfg_mem_ecc_1bit_err" },
327+
{ .int_msk = BIT(13), .msg = "qcn_shap_cfg_mem_ecc_mbit_err" },
328+
{ .int_msk = BIT(14), .msg = "qcn_gp0_barrel_mem_ecc_1bit_err" },
329+
{ .int_msk = BIT(15), .msg = "qcn_gp0_barrel_mem_ecc_mbit_err" },
330+
{ .int_msk = BIT(16), .msg = "qcn_gp1_barrel_mem_ecc_1bit_err" },
331+
{ .int_msk = BIT(17), .msg = "qcn_gp1_barrel_mem_ecc_mbit_err" },
332+
{ .int_msk = BIT(18), .msg = "qcn_gp2_barrel_mem_ecc_1bit_err" },
333+
{ .int_msk = BIT(19), .msg = "qcn_gp2_barrel_mem_ecc_mbit_err" },
334+
{ .int_msk = BIT(20), .msg = "qcn_gp3_barral_mem_ecc_1bit_err" },
335+
{ .int_msk = BIT(21), .msg = "qcn_gp3_barral_mem_ecc_mbit_err" },
336+
{ /* sentinel */ }
337+
};
338+
216339
static void hclge_log_error(struct device *dev,
217340
const struct hclge_hw_error *err_list,
218341
u32 err_sts)
@@ -501,6 +624,47 @@ static int hclge_enable_ppp_error(struct hclge_dev *hdev, bool en)
501624
return ret;
502625
}
503626

627+
int hclge_enable_tm_hw_error(struct hclge_dev *hdev, bool en)
628+
{
629+
struct device *dev = &hdev->pdev->dev;
630+
struct hclge_desc desc;
631+
int ret;
632+
633+
/* enable TM SCH hw errors */
634+
hclge_cmd_setup_basic_desc(&desc, HCLGE_TM_SCH_ECC_INT_EN, false);
635+
if (en)
636+
desc.data[0] = cpu_to_le32(HCLGE_TM_SCH_ECC_ERR_INT_EN);
637+
else
638+
desc.data[0] = 0;
639+
640+
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
641+
if (ret) {
642+
dev_err(dev, "failed(%d) to configure TM SCH errors\n", ret);
643+
return ret;
644+
}
645+
646+
/* enable TM QCN hw errors */
647+
ret = hclge_cmd_query_error(hdev, &desc, HCLGE_TM_QCN_MEM_INT_CFG,
648+
0, 0, 0);
649+
if (ret) {
650+
dev_err(dev, "failed(%d) to read TM QCN CFG status\n", ret);
651+
return ret;
652+
}
653+
654+
hclge_cmd_reuse_desc(&desc, false);
655+
if (en)
656+
desc.data[1] = cpu_to_le32(HCLGE_TM_QCN_MEM_ERR_INT_EN);
657+
else
658+
desc.data[1] = 0;
659+
660+
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
661+
if (ret)
662+
dev_err(dev,
663+
"failed(%d) to configure TM QCN mem errors\n", ret);
664+
665+
return ret;
666+
}
667+
504668
static void hclge_process_common_error(struct hclge_dev *hdev,
505669
enum hclge_err_int_type type)
506670
{
@@ -736,13 +900,135 @@ static void hclge_process_ppp_error(struct hclge_dev *hdev,
736900
ret);
737901
}
738902

903+
static void hclge_process_tm_sch_error(struct hclge_dev *hdev)
904+
{
905+
struct device *dev = &hdev->pdev->dev;
906+
const struct hclge_tm_sch_ecc_info *tm_sch_ecc_info;
907+
struct hclge_desc desc;
908+
u32 ecc_info;
909+
u8 module_no;
910+
u8 ram_no;
911+
int ret;
912+
913+
/* read TM scheduler errors */
914+
ret = hclge_cmd_query_error(hdev, &desc,
915+
HCLGE_TM_SCH_MBIT_ECC_INFO_CMD, 0, 0, 0);
916+
if (ret) {
917+
dev_err(dev, "failed(%d) to read SCH mbit ECC err info\n", ret);
918+
return;
919+
}
920+
ecc_info = le32_to_cpu(desc.data[0]);
921+
922+
ret = hclge_cmd_query_error(hdev, &desc,
923+
HCLGE_TM_SCH_ECC_ERR_RINT_CMD, 0, 0, 0);
924+
if (ret) {
925+
dev_err(dev, "failed(%d) to read SCH ECC err status\n", ret);
926+
return;
927+
}
928+
929+
/* log TM scheduler errors */
930+
if (le32_to_cpu(desc.data[0])) {
931+
hclge_log_error(dev, &hclge_tm_sch_err_int[0],
932+
le32_to_cpu(desc.data[0]));
933+
if (le32_to_cpu(desc.data[0]) & 0x2) {
934+
module_no = (ecc_info >> 20) & 0xF;
935+
ram_no = (ecc_info >> 16) & 0xF;
936+
tm_sch_ecc_info =
937+
&hclge_tm_sch_ecc_err[module_no][ram_no];
938+
dev_warn(dev, "ecc err module:ram=%s\n",
939+
tm_sch_ecc_info->name);
940+
dev_warn(dev, "ecc memory address = 0x%x\n",
941+
ecc_info & 0xFFFF);
942+
}
943+
}
944+
945+
/* clear TM scheduler errors */
946+
ret = hclge_cmd_clear_error(hdev, &desc, NULL, 0, 0);
947+
if (ret) {
948+
dev_err(dev, "failed(%d) to clear TM SCH error status\n", ret);
949+
return;
950+
}
951+
952+
ret = hclge_cmd_query_error(hdev, &desc,
953+
HCLGE_TM_SCH_ECC_ERR_RINT_CE, 0, 0, 0);
954+
if (ret) {
955+
dev_err(dev, "failed(%d) to read SCH CE status\n", ret);
956+
return;
957+
}
958+
959+
ret = hclge_cmd_clear_error(hdev, &desc, NULL, 0, 0);
960+
if (ret) {
961+
dev_err(dev, "failed(%d) to clear TM SCH CE status\n", ret);
962+
return;
963+
}
964+
965+
ret = hclge_cmd_query_error(hdev, &desc,
966+
HCLGE_TM_SCH_ECC_ERR_RINT_NFE, 0, 0, 0);
967+
if (ret) {
968+
dev_err(dev, "failed(%d) to read SCH NFE status\n", ret);
969+
return;
970+
}
971+
972+
ret = hclge_cmd_clear_error(hdev, &desc, NULL, 0, 0);
973+
if (ret) {
974+
dev_err(dev, "failed(%d) to clear TM SCH NFE status\n", ret);
975+
return;
976+
}
977+
978+
ret = hclge_cmd_query_error(hdev, &desc,
979+
HCLGE_TM_SCH_ECC_ERR_RINT_FE, 0, 0, 0);
980+
if (ret) {
981+
dev_err(dev, "failed(%d) to read SCH FE status\n", ret);
982+
return;
983+
}
984+
985+
ret = hclge_cmd_clear_error(hdev, &desc, NULL, 0, 0);
986+
if (ret)
987+
dev_err(dev, "failed(%d) to clear TM SCH FE status\n", ret);
988+
}
989+
990+
static void hclge_process_tm_qcn_error(struct hclge_dev *hdev)
991+
{
992+
struct device *dev = &hdev->pdev->dev;
993+
struct hclge_desc desc;
994+
int ret;
995+
996+
/* read QCN errors */
997+
ret = hclge_cmd_query_error(hdev, &desc,
998+
HCLGE_TM_QCN_MEM_INT_INFO_CMD, 0, 0, 0);
999+
if (ret) {
1000+
dev_err(dev, "failed(%d) to read QCN ECC err status\n", ret);
1001+
return;
1002+
}
1003+
1004+
/* log QCN errors */
1005+
if (le32_to_cpu(desc.data[0]))
1006+
hclge_log_error(dev, &hclge_qcn_ecc_err_int[0],
1007+
le32_to_cpu(desc.data[0]));
1008+
1009+
/* clear QCN errors */
1010+
ret = hclge_cmd_clear_error(hdev, &desc, NULL, 0, 0);
1011+
if (ret)
1012+
dev_err(dev, "failed(%d) to clear QCN error status\n", ret);
1013+
}
1014+
1015+
static void hclge_process_tm_error(struct hclge_dev *hdev,
1016+
enum hclge_err_int_type type)
1017+
{
1018+
hclge_process_tm_sch_error(hdev);
1019+
hclge_process_tm_qcn_error(hdev);
1020+
}
1021+
7391022
static const struct hclge_hw_blk hw_blk[] = {
7401023
{ .msk = BIT(0), .name = "IGU_EGU",
7411024
.enable_error = hclge_enable_igu_egu_error,
7421025
.process_error = hclge_process_igu_egu_error, },
7431026
{ .msk = BIT(5), .name = "COMMON",
7441027
.enable_error = hclge_enable_common_error,
7451028
.process_error = hclge_process_common_error, },
1029+
{ .msk = BIT(4), .name = "TM",
1030+
.enable_error = hclge_enable_tm_hw_error,
1031+
.process_error = hclge_process_tm_error, },
7461032
{ .msk = BIT(1), .name = "PPP",
7471033
.enable_error = hclge_enable_ppp_error,
7481034
.process_error = hclge_process_ppp_error, },

‎drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,8 @@
3737
#define HCLGE_PPP_MPF_ECC_ERR_INT2_EN_MASK 0x003F
3838
#define HCLGE_PPP_MPF_ECC_ERR_INT3_EN 0x003F
3939
#define HCLGE_PPP_MPF_ECC_ERR_INT3_EN_MASK 0x003F
40+
#define HCLGE_TM_SCH_ECC_ERR_INT_EN 0x3
41+
#define HCLGE_TM_QCN_MEM_ERR_INT_EN 0xFFFFFF
4042
#define HCLGE_NCSI_ERR_INT_EN 0x3
4143
#define HCLGE_NCSI_ERR_INT_TYPE 0x9
4244

@@ -76,5 +78,6 @@ struct hclge_hw_error {
7678
};
7779

7880
int hclge_hw_error_set_state(struct hclge_dev *hdev, bool state);
81+
int hclge_enable_tm_hw_error(struct hclge_dev *hdev, bool en);
7982
pci_ers_result_t hclge_process_ras_hw_error(struct hnae3_ae_dev *ae_dev);
8083
#endif

‎drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6881,6 +6881,12 @@ static int hclge_reset_ae_dev(struct hnae3_ae_dev *ae_dev)
68816881
return ret;
68826882
}
68836883

6884+
/* Re-enable the TM hw error interrupts because
6885+
* they get disabled on core/global reset.
6886+
*/
6887+
if (hclge_enable_tm_hw_error(hdev, true))
6888+
dev_err(&pdev->dev, "failed to enable TM hw error interrupts\n");
6889+
68846890
dev_info(&pdev->dev, "Reset done, %s driver initialization finished.\n",
68856891
HCLGE_DRIVER_NAME);
68866892

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