Skip to content

Commit da2d072

Browse files
shijujose4davem330
shijujose4
authored and
davem330
committed
net: hns3: Add enable and process hw errors from PPP
This patch enables and process hw errors from the PPP(Programmable Packet Process) block. Signed-off-by: Shiju Jose <[email protected]> Signed-off-by: Salil Mehta <[email protected]> Signed-off-by: David S. Miller <[email protected]>
1 parent bf1faf9 commit da2d072

File tree

3 files changed

+280
-0
lines changed

3 files changed

+280
-0
lines changed

‎drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -218,6 +218,8 @@ enum hclge_opcode_type {
218218
HCLGE_IGU_COMMON_INT_QUERY = 0x1805,
219219
HCLGE_IGU_COMMON_INT_EN = 0x1806,
220220
HCLGE_IGU_COMMON_INT_CLR = 0x1807,
221+
HCLGE_PPP_CMD0_INT_CMD = 0x2100,
222+
HCLGE_PPP_CMD1_INT_CMD = 0x2101,
221223
HCLGE_NCSI_INT_QUERY = 0x2400,
222224
HCLGE_NCSI_INT_EN = 0x2401,
223225
HCLGE_NCSI_INT_CLR = 0x2402,

‎drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c

Lines changed: 267 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -109,6 +109,110 @@ static const struct hclge_hw_error hclge_ncsi_err_int[] = {
109109
{ /* sentinel */ }
110110
};
111111

112+
static const struct hclge_hw_error hclge_ppp_mpf_int0[] = {
113+
{ .int_msk = BIT(0), .msg = "vf_vlan_ad_mem_ecc_1bit_err" },
114+
{ .int_msk = BIT(1), .msg = "umv_mcast_group_mem_ecc_1bit_err" },
115+
{ .int_msk = BIT(2), .msg = "umv_key_mem0_ecc_1bit_err" },
116+
{ .int_msk = BIT(3), .msg = "umv_key_mem1_ecc_1bit_err" },
117+
{ .int_msk = BIT(4), .msg = "umv_key_mem2_ecc_1bit_err" },
118+
{ .int_msk = BIT(5), .msg = "umv_key_mem3_ecc_1bit_err" },
119+
{ .int_msk = BIT(6), .msg = "umv_ad_mem_ecc_1bit_err" },
120+
{ .int_msk = BIT(7), .msg = "rss_tc_mode_mem_ecc_1bit_err" },
121+
{ .int_msk = BIT(8), .msg = "rss_idt_mem0_ecc_1bit_err" },
122+
{ .int_msk = BIT(9), .msg = "rss_idt_mem1_ecc_1bit_err" },
123+
{ .int_msk = BIT(10), .msg = "rss_idt_mem2_ecc_1bit_err" },
124+
{ .int_msk = BIT(11), .msg = "rss_idt_mem3_ecc_1bit_err" },
125+
{ .int_msk = BIT(12), .msg = "rss_idt_mem4_ecc_1bit_err" },
126+
{ .int_msk = BIT(13), .msg = "rss_idt_mem5_ecc_1bit_err" },
127+
{ .int_msk = BIT(14), .msg = "rss_idt_mem6_ecc_1bit_err" },
128+
{ .int_msk = BIT(15), .msg = "rss_idt_mem7_ecc_1bit_err" },
129+
{ .int_msk = BIT(16), .msg = "rss_idt_mem8_ecc_1bit_err" },
130+
{ .int_msk = BIT(17), .msg = "rss_idt_mem9_ecc_1bit_err" },
131+
{ .int_msk = BIT(18), .msg = "rss_idt_mem10_ecc_1bit_err" },
132+
{ .int_msk = BIT(19), .msg = "rss_idt_mem11_ecc_1bit_err" },
133+
{ .int_msk = BIT(20), .msg = "rss_idt_mem12_ecc_1bit_err" },
134+
{ .int_msk = BIT(21), .msg = "rss_idt_mem13_ecc_1bit_err" },
135+
{ .int_msk = BIT(22), .msg = "rss_idt_mem14_ecc_1bit_err" },
136+
{ .int_msk = BIT(23), .msg = "rss_idt_mem15_ecc_1bit_err" },
137+
{ .int_msk = BIT(24), .msg = "port_vlan_mem_ecc_1bit_err" },
138+
{ .int_msk = BIT(25), .msg = "mcast_linear_table_mem_ecc_1bit_err" },
139+
{ .int_msk = BIT(26), .msg = "mcast_result_mem_ecc_1bit_err" },
140+
{ .int_msk = BIT(27),
141+
.msg = "flow_director_ad_mem0_ecc_1bit_err" },
142+
{ .int_msk = BIT(28),
143+
.msg = "flow_director_ad_mem1_ecc_1bit_err" },
144+
{ .int_msk = BIT(29),
145+
.msg = "rx_vlan_tag_memory_ecc_1bit_err" },
146+
{ .int_msk = BIT(30),
147+
.msg = "Tx_UP_mapping_config_mem_ecc_1bit_err" },
148+
{ /* sentinel */ }
149+
};
150+
151+
static const struct hclge_hw_error hclge_ppp_mpf_int1[] = {
152+
{ .int_msk = BIT(0), .msg = "vf_vlan_ad_mem_ecc_mbit_err" },
153+
{ .int_msk = BIT(1), .msg = "umv_mcast_group_mem_ecc_mbit_err" },
154+
{ .int_msk = BIT(2), .msg = "umv_key_mem0_ecc_mbit_err" },
155+
{ .int_msk = BIT(3), .msg = "umv_key_mem1_ecc_mbit_err" },
156+
{ .int_msk = BIT(4), .msg = "umv_key_mem2_ecc_mbit_err" },
157+
{ .int_msk = BIT(5), .msg = "umv_key_mem3_ecc_mbit_err" },
158+
{ .int_msk = BIT(6), .msg = "umv_ad_mem_ecc_mbit_erre" },
159+
{ .int_msk = BIT(7), .msg = "rss_tc_mode_mem_ecc_mbit_err" },
160+
{ .int_msk = BIT(8), .msg = "rss_idt_mem0_ecc_mbit_err" },
161+
{ .int_msk = BIT(9), .msg = "rss_idt_mem1_ecc_mbit_err" },
162+
{ .int_msk = BIT(10), .msg = "rss_idt_mem2_ecc_mbit_err" },
163+
{ .int_msk = BIT(11), .msg = "rss_idt_mem3_ecc_mbit_err" },
164+
{ .int_msk = BIT(12), .msg = "rss_idt_mem4_ecc_mbit_err" },
165+
{ .int_msk = BIT(13), .msg = "rss_idt_mem5_ecc_mbit_err" },
166+
{ .int_msk = BIT(14), .msg = "rss_idt_mem6_ecc_mbit_err" },
167+
{ .int_msk = BIT(15), .msg = "rss_idt_mem7_ecc_mbit_err" },
168+
{ .int_msk = BIT(16), .msg = "rss_idt_mem8_ecc_mbit_err" },
169+
{ .int_msk = BIT(17), .msg = "rss_idt_mem9_ecc_mbit_err" },
170+
{ .int_msk = BIT(18), .msg = "rss_idt_mem10_ecc_m1bit_err" },
171+
{ .int_msk = BIT(19), .msg = "rss_idt_mem11_ecc_mbit_err" },
172+
{ .int_msk = BIT(20), .msg = "rss_idt_mem12_ecc_mbit_err" },
173+
{ .int_msk = BIT(21), .msg = "rss_idt_mem13_ecc_mbit_err" },
174+
{ .int_msk = BIT(22), .msg = "rss_idt_mem14_ecc_mbit_err" },
175+
{ .int_msk = BIT(23), .msg = "rss_idt_mem15_ecc_mbit_err" },
176+
{ .int_msk = BIT(24), .msg = "port_vlan_mem_ecc_mbit_err" },
177+
{ .int_msk = BIT(25), .msg = "mcast_linear_table_mem_ecc_mbit_err" },
178+
{ .int_msk = BIT(26), .msg = "mcast_result_mem_ecc_mbit_err" },
179+
{ .int_msk = BIT(27),
180+
.msg = "flow_director_ad_mem0_ecc_mbit_err" },
181+
{ .int_msk = BIT(28),
182+
.msg = "flow_director_ad_mem1_ecc_mbit_err" },
183+
{ .int_msk = BIT(29),
184+
.msg = "rx_vlan_tag_memory_ecc_mbit_err" },
185+
{ .int_msk = BIT(30),
186+
.msg = "Tx_UP_mapping_config_mem_ecc_mbit_err" },
187+
{ /* sentinel */ }
188+
};
189+
190+
static const struct hclge_hw_error hclge_ppp_pf_int[] = {
191+
{ .int_msk = BIT(0), .msg = "Tx_vlan_tag_err" },
192+
{ .int_msk = BIT(1), .msg = "rss_list_tc_unassigned_queue_err" },
193+
{ /* sentinel */ }
194+
};
195+
196+
static const struct hclge_hw_error hclge_ppp_mpf_int2[] = {
197+
{ .int_msk = BIT(0), .msg = "hfs_fifo_mem_ecc_1bit_err" },
198+
{ .int_msk = BIT(1), .msg = "rslt_descr_fifo_mem_ecc_1bit_err" },
199+
{ .int_msk = BIT(2), .msg = "tx_vlan_tag_mem_ecc_1bit_err" },
200+
{ .int_msk = BIT(3), .msg = "FD_CN0_memory_ecc_1bit_err" },
201+
{ .int_msk = BIT(4), .msg = "FD_CN1_memory_ecc_1bit_err" },
202+
{ .int_msk = BIT(5), .msg = "GRO_AD_memory_ecc_1bit_err" },
203+
{ /* sentinel */ }
204+
};
205+
206+
static const struct hclge_hw_error hclge_ppp_mpf_int3[] = {
207+
{ .int_msk = BIT(0), .msg = "hfs_fifo_mem_ecc_mbit_err" },
208+
{ .int_msk = BIT(1), .msg = "rslt_descr_fifo_mem_ecc_mbit_err" },
209+
{ .int_msk = BIT(2), .msg = "tx_vlan_tag_mem_ecc_mbit_err" },
210+
{ .int_msk = BIT(3), .msg = "FD_CN0_memory_ecc_mbit_err" },
211+
{ .int_msk = BIT(4), .msg = "FD_CN1_memory_ecc_mbit_err" },
212+
{ .int_msk = BIT(5), .msg = "GRO_AD_memory_ecc_mbit_err" },
213+
{ /* sentinel */ }
214+
};
215+
112216
static void hclge_log_error(struct device *dev,
113217
const struct hclge_hw_error *err_list,
114218
u32 err_sts)
@@ -322,6 +426,81 @@ static int hclge_enable_igu_egu_error(struct hclge_dev *hdev, bool en)
322426
return ret;
323427
}
324428

429+
static int hclge_enable_ppp_error_interrupt(struct hclge_dev *hdev, u32 cmd,
430+
bool en)
431+
{
432+
struct device *dev = &hdev->pdev->dev;
433+
struct hclge_desc desc[2];
434+
int ret;
435+
436+
/* enable/disable PPP error interrupts */
437+
hclge_cmd_setup_basic_desc(&desc[0], cmd, false);
438+
desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
439+
hclge_cmd_setup_basic_desc(&desc[1], cmd, false);
440+
441+
if (cmd == HCLGE_PPP_CMD0_INT_CMD) {
442+
if (en) {
443+
desc[0].data[0] =
444+
cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT0_EN);
445+
desc[0].data[1] =
446+
cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT1_EN);
447+
} else {
448+
desc[0].data[0] = 0;
449+
desc[0].data[1] = 0;
450+
}
451+
desc[1].data[0] =
452+
cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT0_EN_MASK);
453+
desc[1].data[1] =
454+
cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT1_EN_MASK);
455+
} else if (cmd == HCLGE_PPP_CMD1_INT_CMD) {
456+
if (en) {
457+
desc[0].data[0] =
458+
cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT2_EN);
459+
desc[0].data[1] =
460+
cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT3_EN);
461+
} else {
462+
desc[0].data[0] = 0;
463+
desc[0].data[1] = 0;
464+
}
465+
desc[1].data[0] =
466+
cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT2_EN_MASK);
467+
desc[1].data[1] =
468+
cpu_to_le32(HCLGE_PPP_MPF_ECC_ERR_INT3_EN_MASK);
469+
}
470+
471+
ret = hclge_cmd_send(&hdev->hw, &desc[0], 2);
472+
if (ret)
473+
dev_err(dev,
474+
"failed(%d) to enable/disable PPP error interrupts\n",
475+
ret);
476+
477+
return ret;
478+
}
479+
480+
static int hclge_enable_ppp_error(struct hclge_dev *hdev, bool en)
481+
{
482+
struct device *dev = &hdev->pdev->dev;
483+
int ret;
484+
485+
ret = hclge_enable_ppp_error_interrupt(hdev, HCLGE_PPP_CMD0_INT_CMD,
486+
en);
487+
if (ret) {
488+
dev_err(dev,
489+
"failed(%d) to enable/disable PPP error intr 0,1\n",
490+
ret);
491+
return ret;
492+
}
493+
494+
ret = hclge_enable_ppp_error_interrupt(hdev, HCLGE_PPP_CMD1_INT_CMD,
495+
en);
496+
if (ret)
497+
dev_err(dev,
498+
"failed(%d) to enable/disable PPP error intr 2,3\n",
499+
ret);
500+
501+
return ret;
502+
}
503+
325504
static void hclge_process_common_error(struct hclge_dev *hdev,
326505
enum hclge_err_int_type type)
327506
{
@@ -472,13 +651,101 @@ static void hclge_process_igu_egu_error(struct hclge_dev *hdev,
472651
hclge_process_ncsi_error(hdev, HCLGE_ERR_INT_RAS_NFE);
473652
}
474653

654+
static int hclge_log_and_clear_ppp_error(struct hclge_dev *hdev, u32 cmd,
655+
enum hclge_err_int_type int_type)
656+
{
657+
enum hnae3_reset_type reset_level = HNAE3_NONE_RESET;
658+
struct device *dev = &hdev->pdev->dev;
659+
const struct hclge_hw_error *hw_err_lst1, *hw_err_lst2, *hw_err_lst3;
660+
struct hclge_desc desc[2];
661+
u32 err_sts;
662+
int ret;
663+
664+
/* read PPP INT sts */
665+
ret = hclge_cmd_query_error(hdev, &desc[0], cmd,
666+
HCLGE_CMD_FLAG_NEXT, 5, int_type);
667+
if (ret) {
668+
dev_err(dev, "failed(=%d) to query PPP interrupt status\n",
669+
ret);
670+
return -EIO;
671+
}
672+
673+
/* log error */
674+
if (cmd == HCLGE_PPP_CMD0_INT_CMD) {
675+
hw_err_lst1 = &hclge_ppp_mpf_int0[0];
676+
hw_err_lst2 = &hclge_ppp_mpf_int1[0];
677+
hw_err_lst3 = &hclge_ppp_pf_int[0];
678+
} else if (cmd == HCLGE_PPP_CMD1_INT_CMD) {
679+
hw_err_lst1 = &hclge_ppp_mpf_int2[0];
680+
hw_err_lst2 = &hclge_ppp_mpf_int3[0];
681+
} else {
682+
dev_err(dev, "invalid command(=%d)\n", cmd);
683+
return -EINVAL;
684+
}
685+
686+
err_sts = le32_to_cpu(desc[0].data[2]);
687+
if (err_sts) {
688+
hclge_log_error(dev, hw_err_lst1, err_sts);
689+
reset_level = HNAE3_FUNC_RESET;
690+
}
691+
692+
err_sts = le32_to_cpu(desc[0].data[3]);
693+
if (err_sts) {
694+
hclge_log_error(dev, hw_err_lst2, err_sts);
695+
reset_level = HNAE3_FUNC_RESET;
696+
}
697+
698+
err_sts = (le32_to_cpu(desc[0].data[4]) >> 8) & 0x3;
699+
if (err_sts) {
700+
hclge_log_error(dev, hw_err_lst3, err_sts);
701+
reset_level = HNAE3_FUNC_RESET;
702+
}
703+
704+
/* clear PPP INT */
705+
ret = hclge_cmd_clear_error(hdev, &desc[0], NULL, 0,
706+
HCLGE_CMD_FLAG_NEXT);
707+
if (ret) {
708+
dev_err(dev, "failed(=%d) to clear PPP interrupt status\n",
709+
ret);
710+
return -EIO;
711+
}
712+
713+
return 0;
714+
}
715+
716+
static void hclge_process_ppp_error(struct hclge_dev *hdev,
717+
enum hclge_err_int_type int_type)
718+
{
719+
struct device *dev = &hdev->pdev->dev;
720+
int ret;
721+
722+
/* read PPP INT0,1 sts */
723+
ret = hclge_log_and_clear_ppp_error(hdev, HCLGE_PPP_CMD0_INT_CMD,
724+
int_type);
725+
if (ret < 0) {
726+
dev_err(dev, "failed(=%d) to clear PPP interrupt 0,1 status\n",
727+
ret);
728+
return;
729+
}
730+
731+
/* read err PPP INT2,3 sts */
732+
ret = hclge_log_and_clear_ppp_error(hdev, HCLGE_PPP_CMD1_INT_CMD,
733+
int_type);
734+
if (ret < 0)
735+
dev_err(dev, "failed(=%d) to clear PPP interrupt 2,3 status\n",
736+
ret);
737+
}
738+
475739
static const struct hclge_hw_blk hw_blk[] = {
476740
{ .msk = BIT(0), .name = "IGU_EGU",
477741
.enable_error = hclge_enable_igu_egu_error,
478742
.process_error = hclge_process_igu_egu_error, },
479743
{ .msk = BIT(5), .name = "COMMON",
480744
.enable_error = hclge_enable_common_error,
481745
.process_error = hclge_process_common_error, },
746+
{ .msk = BIT(1), .name = "PPP",
747+
.enable_error = hclge_enable_ppp_error,
748+
.process_error = hclge_process_ppp_error, },
482749
{ /* sentinel */ }
483750
};
484751

‎drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,16 @@
2727
#define HCLGE_IGU_ERR_INT_EN_MASK 0x000F
2828
#define HCLGE_IGU_TNL_ERR_INT_EN 0x0002AABF
2929
#define HCLGE_IGU_TNL_ERR_INT_EN_MASK 0x003F
30+
#define HCLGE_PPP_MPF_ECC_ERR_INT0_EN 0xFFFFFFFF
31+
#define HCLGE_PPP_MPF_ECC_ERR_INT0_EN_MASK 0xFFFFFFFF
32+
#define HCLGE_PPP_MPF_ECC_ERR_INT1_EN 0xFFFFFFFF
33+
#define HCLGE_PPP_MPF_ECC_ERR_INT1_EN_MASK 0xFFFFFFFF
34+
#define HCLGE_PPP_PF_ERR_INT_EN 0x0003
35+
#define HCLGE_PPP_PF_ERR_INT_EN_MASK 0x0003
36+
#define HCLGE_PPP_MPF_ECC_ERR_INT2_EN 0x003F
37+
#define HCLGE_PPP_MPF_ECC_ERR_INT2_EN_MASK 0x003F
38+
#define HCLGE_PPP_MPF_ECC_ERR_INT3_EN 0x003F
39+
#define HCLGE_PPP_MPF_ECC_ERR_INT3_EN_MASK 0x003F
3040
#define HCLGE_NCSI_ERR_INT_EN 0x3
3141
#define HCLGE_NCSI_ERR_INT_TYPE 0x9
3242

@@ -43,6 +53,7 @@
4353
#define HCLGE_TQP_IMP_ERR_CLR_MASK 0x0FFF0001
4454
#define HCLGE_IGU_COM_INT_MASK 0xF
4555
#define HCLGE_IGU_EGU_TNL_INT_MASK 0x3F
56+
#define HCLGE_PPP_PF_INT_MASK 0x100
4657

4758
enum hclge_err_int_type {
4859
HCLGE_ERR_INT_MSIX = 0,

0 commit comments

Comments
 (0)