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Merge tag 'drm-fixes-for-v4.17-rc1' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie: "One omap, and one alsa pm fix (we merged the breaking patch via drm tree). Otherwise it's two bunches of amdgpu fixes, removing an unneeded file, some DC fixes, HDMI audio regression fix, and some vega12 fixes" * tag 'drm-fixes-for-v4.17-rc1' of git://people.freedesktop.org/~airlied/linux: (27 commits) Revert "drm/amd/display: disable CRTCs with NULL FB on their primary plane (V2)" Revert "drm/amd/display: fix dereferencing possible ERR_PTR()" drm/amd/display: Fix regamma not affecting full-intensity color values drm/amd/display: Fix FBC text console corruption drm/amd/display: Only register backlight device if embedded panel connected drm/amd/display: fix brightness level after resume from suspend drm/amd/display: HDMI has no sound after Panel power off/on drm/amdgpu: add MP1 and THM hw ip base reg offset drm/amdgpu: fix null pointer panic with direct fw loading on gpu reset drm/radeon: add PX quirk for Asus K73TK drm/omap: fix crash if there's no video PLL drm/amdgpu: Fix memory leaks at amdgpu_init() error path drm/amdgpu: Fix PCIe lane width calculation drm/radeon: Fix PCIe lane width calculation drm/amdgpu/si: implement get/set pcie_lanes asic callback drm/amdgpu: Add support for SRBM selection v3 Revert "drm/amdgpu: Don't change preferred domian when fallback GTT v5" drm/amd/powerply: fix power reading on Fiji drm/amd/powerplay: Enable ACG SS feature drm/amdgpu/sdma: fix mask in emit_pipeline_sync ...
2 parents affb028 + a10beab commit 16e205c

40 files changed

+432
-1640
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -890,6 +890,7 @@ struct amdgpu_gfx_funcs {
890890
void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields);
891891
void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
892892
void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
893+
void (*select_me_pipe_q)(struct amdgpu_device *adev, u32 me, u32 pipe, u32 queue);
893894
};
894895

895896
struct amdgpu_ngg_buf {
@@ -1378,6 +1379,7 @@ enum amd_hw_ip_block_type {
13781379
ATHUB_HWIP,
13791380
NBIO_HWIP,
13801381
MP0_HWIP,
1382+
MP1_HWIP,
13811383
UVD_HWIP,
13821384
VCN_HWIP = UVD_HWIP,
13831385
VCE_HWIP,
@@ -1387,6 +1389,7 @@ enum amd_hw_ip_block_type {
13871389
SMUIO_HWIP,
13881390
PWR_HWIP,
13891391
NBIF_HWIP,
1392+
THM_HWIP,
13901393
MAX_HWIP
13911394
};
13921395

@@ -1812,6 +1815,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
18121815
#define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
18131816
#define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
18141817
#define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
1818+
#define amdgpu_gfx_select_me_pipe_q(adev, me, pipe, q) (adev)->gfx.funcs->select_me_pipe_q((adev), (me), (pipe), (q))
18151819

18161820
/* Common functions */
18171821
int amdgpu_device_gpu_recover(struct amdgpu_device *adev,

‎drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

Lines changed: 40 additions & 77 deletions
Original file line numberDiff line numberDiff line change
@@ -64,16 +64,21 @@ int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
6464

6565
#if defined(CONFIG_DEBUG_FS)
6666

67-
static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
68-
size_t size, loff_t *pos)
67+
68+
static int amdgpu_debugfs_process_reg_op(bool read, struct file *f,
69+
char __user *buf, size_t size, loff_t *pos)
6970
{
7071
struct amdgpu_device *adev = file_inode(f)->i_private;
7172
ssize_t result = 0;
7273
int r;
73-
bool pm_pg_lock, use_bank;
74-
unsigned instance_bank, sh_bank, se_bank;
74+
bool pm_pg_lock, use_bank, use_ring;
75+
unsigned instance_bank, sh_bank, se_bank, me, pipe, queue;
7576

76-
if (size & 0x3 || *pos & 0x3)
77+
pm_pg_lock = use_bank = use_ring = false;
78+
instance_bank = sh_bank = se_bank = me = pipe = queue = 0;
79+
80+
if (size & 0x3 || *pos & 0x3 ||
81+
((*pos & (1ULL << 62)) && (*pos & (1ULL << 61))))
7782
return -EINVAL;
7883

7984
/* are we reading registers for which a PG lock is necessary? */
@@ -91,8 +96,15 @@ static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
9196
if (instance_bank == 0x3FF)
9297
instance_bank = 0xFFFFFFFF;
9398
use_bank = 1;
99+
} else if (*pos & (1ULL << 61)) {
100+
101+
me = (*pos & GENMASK_ULL(33, 24)) >> 24;
102+
pipe = (*pos & GENMASK_ULL(43, 34)) >> 34;
103+
queue = (*pos & GENMASK_ULL(53, 44)) >> 44;
104+
105+
use_ring = 1;
94106
} else {
95-
use_bank = 0;
107+
use_bank = use_ring = 0;
96108
}
97109

98110
*pos &= (1UL << 22) - 1;
@@ -104,6 +116,9 @@ static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
104116
mutex_lock(&adev->grbm_idx_mutex);
105117
amdgpu_gfx_select_se_sh(adev, se_bank,
106118
sh_bank, instance_bank);
119+
} else if (use_ring) {
120+
mutex_lock(&adev->srbm_mutex);
121+
amdgpu_gfx_select_me_pipe_q(adev, me, pipe, queue);
107122
}
108123

109124
if (pm_pg_lock)
@@ -115,8 +130,14 @@ static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
115130
if (*pos > adev->rmmio_size)
116131
goto end;
117132

118-
value = RREG32(*pos >> 2);
119-
r = put_user(value, (uint32_t *)buf);
133+
if (read) {
134+
value = RREG32(*pos >> 2);
135+
r = put_user(value, (uint32_t *)buf);
136+
} else {
137+
r = get_user(value, (uint32_t *)buf);
138+
if (!r)
139+
WREG32(*pos >> 2, value);
140+
}
120141
if (r) {
121142
result = r;
122143
goto end;
@@ -132,6 +153,9 @@ static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
132153
if (use_bank) {
133154
amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
134155
mutex_unlock(&adev->grbm_idx_mutex);
156+
} else if (use_ring) {
157+
amdgpu_gfx_select_me_pipe_q(adev, 0, 0, 0);
158+
mutex_unlock(&adev->srbm_mutex);
135159
}
136160

137161
if (pm_pg_lock)
@@ -140,78 +164,17 @@ static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
140164
return result;
141165
}
142166

167+
168+
static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
169+
size_t size, loff_t *pos)
170+
{
171+
return amdgpu_debugfs_process_reg_op(true, f, buf, size, pos);
172+
}
173+
143174
static ssize_t amdgpu_debugfs_regs_write(struct file *f, const char __user *buf,
144175
size_t size, loff_t *pos)
145176
{
146-
struct amdgpu_device *adev = file_inode(f)->i_private;
147-
ssize_t result = 0;
148-
int r;
149-
bool pm_pg_lock, use_bank;
150-
unsigned instance_bank, sh_bank, se_bank;
151-
152-
if (size & 0x3 || *pos & 0x3)
153-
return -EINVAL;
154-
155-
/* are we reading registers for which a PG lock is necessary? */
156-
pm_pg_lock = (*pos >> 23) & 1;
157-
158-
if (*pos & (1ULL << 62)) {
159-
se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
160-
sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
161-
instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
162-
163-
if (se_bank == 0x3FF)
164-
se_bank = 0xFFFFFFFF;
165-
if (sh_bank == 0x3FF)
166-
sh_bank = 0xFFFFFFFF;
167-
if (instance_bank == 0x3FF)
168-
instance_bank = 0xFFFFFFFF;
169-
use_bank = 1;
170-
} else {
171-
use_bank = 0;
172-
}
173-
174-
*pos &= (1UL << 22) - 1;
175-
176-
if (use_bank) {
177-
if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
178-
(se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
179-
return -EINVAL;
180-
mutex_lock(&adev->grbm_idx_mutex);
181-
amdgpu_gfx_select_se_sh(adev, se_bank,
182-
sh_bank, instance_bank);
183-
}
184-
185-
if (pm_pg_lock)
186-
mutex_lock(&adev->pm.mutex);
187-
188-
while (size) {
189-
uint32_t value;
190-
191-
if (*pos > adev->rmmio_size)
192-
return result;
193-
194-
r = get_user(value, (uint32_t *)buf);
195-
if (r)
196-
return r;
197-
198-
WREG32(*pos >> 2, value);
199-
200-
result += 4;
201-
buf += 4;
202-
*pos += 4;
203-
size -= 4;
204-
}
205-
206-
if (use_bank) {
207-
amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
208-
mutex_unlock(&adev->grbm_idx_mutex);
209-
}
210-
211-
if (pm_pg_lock)
212-
mutex_unlock(&adev->pm.mutex);
213-
214-
return result;
177+
return amdgpu_debugfs_process_reg_op(false, f, (char __user *)buf, size, pos);
215178
}
216179

217180
static ssize_t amdgpu_debugfs_regs_pcie_read(struct file *f, char __user *buf,

‎drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -922,6 +922,11 @@ static int __init amdgpu_init(void)
922922
{
923923
int r;
924924

925+
if (vgacon_text_force()) {
926+
DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
927+
return -EINVAL;
928+
}
929+
925930
r = amdgpu_sync_init();
926931
if (r)
927932
goto error_sync;
@@ -930,10 +935,6 @@ static int __init amdgpu_init(void)
930935
if (r)
931936
goto error_fence;
932937

933-
if (vgacon_text_force()) {
934-
DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
935-
return -EINVAL;
936-
}
937938
DRM_INFO("amdgpu kernel modesetting enabled.\n");
938939
driver = &kms_driver;
939940
pdriver = &amdgpu_kms_pci_driver;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -410,6 +410,7 @@ int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
410410
int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
411411
unsigned num_hw_submission)
412412
{
413+
long timeout;
413414
int r;
414415

415416
/* Check that num_hw_submission is a power of two */
@@ -433,11 +434,16 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
433434

434435
/* No need to setup the GPU scheduler for KIQ ring */
435436
if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) {
437+
/* for non-sriov case, no timeout enforce on compute ring */
438+
if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
439+
&& !amdgpu_sriov_vf(ring->adev))
440+
timeout = MAX_SCHEDULE_TIMEOUT;
441+
else
442+
timeout = msecs_to_jiffies(amdgpu_lockup_timeout);
443+
436444
r = drm_sched_init(&ring->sched, &amdgpu_sched_ops,
437445
num_hw_submission, amdgpu_job_hang_limit,
438-
(ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) ?
439-
MAX_SCHEDULE_TIMEOUT : msecs_to_jiffies(amdgpu_lockup_timeout),
440-
ring->name);
446+
timeout, ring->name);
441447
if (r) {
442448
DRM_ERROR("Failed to create scheduler on ring %s.\n",
443449
ring->name);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c

Lines changed: 14 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -56,11 +56,23 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
5656
alignment = PAGE_SIZE;
5757
}
5858

59+
retry:
5960
r = amdgpu_bo_create(adev, size, alignment, initial_domain,
6061
flags, type, resv, &bo);
6162
if (r) {
62-
DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
63-
size, initial_domain, alignment, r);
63+
if (r != -ERESTARTSYS) {
64+
if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
65+
flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
66+
goto retry;
67+
}
68+
69+
if (initial_domain == AMDGPU_GEM_DOMAIN_VRAM) {
70+
initial_domain |= AMDGPU_GEM_DOMAIN_GTT;
71+
goto retry;
72+
}
73+
DRM_DEBUG("Failed to allocate GEM object (%ld, %d, %u, %d)\n",
74+
size, initial_domain, alignment, r);
75+
}
6476
return r;
6577
}
6678
*obj = &bo->gem_base;

‎drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

Lines changed: 3 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -356,7 +356,6 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, unsigned long size,
356356
struct amdgpu_bo *bo;
357357
unsigned long page_align;
358358
size_t acc_size;
359-
u32 domains;
360359
int r;
361360

362361
page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
@@ -418,23 +417,12 @@ static int amdgpu_bo_do_create(struct amdgpu_device *adev, unsigned long size,
418417
#endif
419418

420419
bo->tbo.bdev = &adev->mman.bdev;
421-
domains = bo->preferred_domains;
422-
retry:
423-
amdgpu_ttm_placement_from_domain(bo, domains);
420+
amdgpu_ttm_placement_from_domain(bo, domain);
421+
424422
r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type,
425423
&bo->placement, page_align, &ctx, acc_size,
426424
NULL, resv, &amdgpu_ttm_bo_destroy);
427-
428-
if (unlikely(r && r != -ERESTARTSYS)) {
429-
if (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
430-
bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
431-
goto retry;
432-
} else if (domains != bo->preferred_domains) {
433-
domains = bo->allowed_domains;
434-
goto retry;
435-
}
436-
}
437-
if (unlikely(r))
425+
if (unlikely(r != 0))
438426
return r;
439427

440428
if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&

‎drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -505,6 +505,9 @@ static int psp_resume(void *handle)
505505

506506
int psp_gpu_reset(struct amdgpu_device *adev)
507507
{
508+
if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
509+
return 0;
510+
508511
return psp_mode1_reset(&adev->psp);
509512
}
510513

‎drivers/gpu/drm/amd/amdgpu/cik_sdma.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -859,7 +859,7 @@ static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
859859
amdgpu_ring_write(ring, addr & 0xfffffffc);
860860
amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
861861
amdgpu_ring_write(ring, seq); /* reference */
862-
amdgpu_ring_write(ring, 0xfffffff); /* mask */
862+
amdgpu_ring_write(ring, 0xffffffff); /* mask */
863863
amdgpu_ring_write(ring, (0xfff << 16) | 4); /* retry count, poll interval */
864864
}
865865

‎drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3061,11 +3061,18 @@ static void gfx_v6_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
30613061
start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
30623062
}
30633063

3064+
static void gfx_v6_0_select_me_pipe_q(struct amdgpu_device *adev,
3065+
u32 me, u32 pipe, u32 q)
3066+
{
3067+
DRM_INFO("Not implemented\n");
3068+
}
3069+
30643070
static const struct amdgpu_gfx_funcs gfx_v6_0_gfx_funcs = {
30653071
.get_gpu_clock_counter = &gfx_v6_0_get_gpu_clock_counter,
30663072
.select_se_sh = &gfx_v6_0_select_se_sh,
30673073
.read_wave_data = &gfx_v6_0_read_wave_data,
30683074
.read_wave_sgprs = &gfx_v6_0_read_wave_sgprs,
3075+
.select_me_pipe_q = &gfx_v6_0_select_me_pipe_q
30693076
};
30703077

30713078
static int gfx_v6_0_early_init(void *handle)

‎drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4270,11 +4270,18 @@ static void gfx_v7_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
42704270
start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
42714271
}
42724272

4273+
static void gfx_v7_0_select_me_pipe_q(struct amdgpu_device *adev,
4274+
u32 me, u32 pipe, u32 q)
4275+
{
4276+
cik_srbm_select(adev, me, pipe, q, 0);
4277+
}
4278+
42734279
static const struct amdgpu_gfx_funcs gfx_v7_0_gfx_funcs = {
42744280
.get_gpu_clock_counter = &gfx_v7_0_get_gpu_clock_counter,
42754281
.select_se_sh = &gfx_v7_0_select_se_sh,
42764282
.read_wave_data = &gfx_v7_0_read_wave_data,
42774283
.read_wave_sgprs = &gfx_v7_0_read_wave_sgprs,
4284+
.select_me_pipe_q = &gfx_v7_0_select_me_pipe_q
42784285
};
42794286

42804287
static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = {

‎drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3475,6 +3475,12 @@ static void gfx_v8_0_select_se_sh(struct amdgpu_device *adev,
34753475
WREG32(mmGRBM_GFX_INDEX, data);
34763476
}
34773477

3478+
static void gfx_v8_0_select_me_pipe_q(struct amdgpu_device *adev,
3479+
u32 me, u32 pipe, u32 q)
3480+
{
3481+
vi_srbm_select(adev, me, pipe, q, 0);
3482+
}
3483+
34783484
static u32 gfx_v8_0_get_rb_active_bitmap(struct amdgpu_device *adev)
34793485
{
34803486
u32 data, mask;
@@ -5442,6 +5448,7 @@ static const struct amdgpu_gfx_funcs gfx_v8_0_gfx_funcs = {
54425448
.select_se_sh = &gfx_v8_0_select_se_sh,
54435449
.read_wave_data = &gfx_v8_0_read_wave_data,
54445450
.read_wave_sgprs = &gfx_v8_0_read_wave_sgprs,
5451+
.select_me_pipe_q = &gfx_v8_0_select_me_pipe_q
54455452
};
54465453

54475454
static int gfx_v8_0_early_init(void *handle)

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