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Srinivas-Kandagatlavijay-suman
Srinivas-Kandagatla
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vijay-suman
committed
ASoC: codecs:lpass-wsa-macro: Fix logic of enabling vi channels
commit 7648beb65600220996ebb2da207610b1ff9b735e upstream. Existing code only configures one of WSA_MACRO_TX0 or WSA_MACRO_TX1 paths eventhough we enable both of them. Fix this bug by adding proper checks and rearranging some of the common code to able to allow setting both TX0 and TX1 paths Without this patch only one channel gets enabled in VI path instead of 2 channels. End result would be 1 channel recording instead of 2. Fixes: 2c4066e ("ASoC: codecs: lpass-wsa-macro: add dapm widgets and route") Cc: [email protected] Co-developed-by: Manikantan R <[email protected]> Signed-off-by: Manikantan R <[email protected]> Signed-off-by: Srinivas Kandagatla <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Mark Brown <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]> (cherry picked from commit 442a0ab6a4e95e64430b4ae75388929ec5d2e615) Signed-off-by: Vijayendra Suman <[email protected]>
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‎sound/soc/codecs/lpass-wsa-macro.c

Lines changed: 63 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -1146,6 +1146,67 @@ static void wsa_macro_mclk_enable(struct wsa_macro *wsa, bool mclk_enable)
11461146
}
11471147
}
11481148

1149+
static void wsa_macro_enable_disable_vi_sense(struct snd_soc_component *component, bool enable,
1150+
u32 tx_reg0, u32 tx_reg1, u32 val)
1151+
{
1152+
if (enable) {
1153+
/* Enable V&I sensing */
1154+
snd_soc_component_update_bits(component, tx_reg0,
1155+
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1156+
CDC_WSA_TX_SPKR_PROT_RESET);
1157+
snd_soc_component_update_bits(component, tx_reg1,
1158+
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1159+
CDC_WSA_TX_SPKR_PROT_RESET);
1160+
snd_soc_component_update_bits(component, tx_reg0,
1161+
CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK,
1162+
val);
1163+
snd_soc_component_update_bits(component, tx_reg1,
1164+
CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK,
1165+
val);
1166+
snd_soc_component_update_bits(component, tx_reg0,
1167+
CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1168+
CDC_WSA_TX_SPKR_PROT_CLK_ENABLE);
1169+
snd_soc_component_update_bits(component, tx_reg1,
1170+
CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1171+
CDC_WSA_TX_SPKR_PROT_CLK_ENABLE);
1172+
snd_soc_component_update_bits(component, tx_reg0,
1173+
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1174+
CDC_WSA_TX_SPKR_PROT_NO_RESET);
1175+
snd_soc_component_update_bits(component, tx_reg1,
1176+
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1177+
CDC_WSA_TX_SPKR_PROT_NO_RESET);
1178+
} else {
1179+
snd_soc_component_update_bits(component, tx_reg0,
1180+
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1181+
CDC_WSA_TX_SPKR_PROT_RESET);
1182+
snd_soc_component_update_bits(component, tx_reg1,
1183+
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1184+
CDC_WSA_TX_SPKR_PROT_RESET);
1185+
snd_soc_component_update_bits(component, tx_reg0,
1186+
CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1187+
CDC_WSA_TX_SPKR_PROT_CLK_DISABLE);
1188+
snd_soc_component_update_bits(component, tx_reg1,
1189+
CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1190+
CDC_WSA_TX_SPKR_PROT_CLK_DISABLE);
1191+
}
1192+
}
1193+
1194+
static void wsa_macro_enable_disable_vi_feedback(struct snd_soc_component *component,
1195+
bool enable, u32 rate)
1196+
{
1197+
struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1198+
1199+
if (test_bit(WSA_MACRO_TX0, &wsa->active_ch_mask[WSA_MACRO_AIF_VI]))
1200+
wsa_macro_enable_disable_vi_sense(component, enable,
1201+
CDC_WSA_TX0_SPKR_PROT_PATH_CTL,
1202+
CDC_WSA_TX1_SPKR_PROT_PATH_CTL, rate);
1203+
1204+
if (test_bit(WSA_MACRO_TX1, &wsa->active_ch_mask[WSA_MACRO_AIF_VI]))
1205+
wsa_macro_enable_disable_vi_sense(component, enable,
1206+
CDC_WSA_TX2_SPKR_PROT_PATH_CTL,
1207+
CDC_WSA_TX3_SPKR_PROT_PATH_CTL, rate);
1208+
}
1209+
11491210
static int wsa_macro_mclk_event(struct snd_soc_dapm_widget *w,
11501211
struct snd_kcontrol *kcontrol, int event)
11511212
{
@@ -1162,7 +1223,6 @@ static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w,
11621223
{
11631224
struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
11641225
struct wsa_macro *wsa = snd_soc_component_get_drvdata(component);
1165-
u32 tx_reg0, tx_reg1;
11661226
u32 rate_val;
11671227

11681228
switch (wsa->pcm_rate_vi) {
@@ -1186,56 +1246,14 @@ static int wsa_macro_enable_vi_feedback(struct snd_soc_dapm_widget *w,
11861246
break;
11871247
}
11881248

1189-
if (test_bit(WSA_MACRO_TX0, &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
1190-
tx_reg0 = CDC_WSA_TX0_SPKR_PROT_PATH_CTL;
1191-
tx_reg1 = CDC_WSA_TX1_SPKR_PROT_PATH_CTL;
1192-
} else if (test_bit(WSA_MACRO_TX1, &wsa->active_ch_mask[WSA_MACRO_AIF_VI])) {
1193-
tx_reg0 = CDC_WSA_TX2_SPKR_PROT_PATH_CTL;
1194-
tx_reg1 = CDC_WSA_TX3_SPKR_PROT_PATH_CTL;
1195-
}
1196-
11971249
switch (event) {
11981250
case SND_SOC_DAPM_POST_PMU:
11991251
/* Enable V&I sensing */
1200-
snd_soc_component_update_bits(component, tx_reg0,
1201-
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1202-
CDC_WSA_TX_SPKR_PROT_RESET);
1203-
snd_soc_component_update_bits(component, tx_reg1,
1204-
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1205-
CDC_WSA_TX_SPKR_PROT_RESET);
1206-
snd_soc_component_update_bits(component, tx_reg0,
1207-
CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK,
1208-
rate_val);
1209-
snd_soc_component_update_bits(component, tx_reg1,
1210-
CDC_WSA_TX_SPKR_PROT_PCM_RATE_MASK,
1211-
rate_val);
1212-
snd_soc_component_update_bits(component, tx_reg0,
1213-
CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1214-
CDC_WSA_TX_SPKR_PROT_CLK_ENABLE);
1215-
snd_soc_component_update_bits(component, tx_reg1,
1216-
CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1217-
CDC_WSA_TX_SPKR_PROT_CLK_ENABLE);
1218-
snd_soc_component_update_bits(component, tx_reg0,
1219-
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1220-
CDC_WSA_TX_SPKR_PROT_NO_RESET);
1221-
snd_soc_component_update_bits(component, tx_reg1,
1222-
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1223-
CDC_WSA_TX_SPKR_PROT_NO_RESET);
1252+
wsa_macro_enable_disable_vi_feedback(component, true, rate_val);
12241253
break;
12251254
case SND_SOC_DAPM_POST_PMD:
12261255
/* Disable V&I sensing */
1227-
snd_soc_component_update_bits(component, tx_reg0,
1228-
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1229-
CDC_WSA_TX_SPKR_PROT_RESET);
1230-
snd_soc_component_update_bits(component, tx_reg1,
1231-
CDC_WSA_TX_SPKR_PROT_RESET_MASK,
1232-
CDC_WSA_TX_SPKR_PROT_RESET);
1233-
snd_soc_component_update_bits(component, tx_reg0,
1234-
CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1235-
CDC_WSA_TX_SPKR_PROT_CLK_DISABLE);
1236-
snd_soc_component_update_bits(component, tx_reg1,
1237-
CDC_WSA_TX_SPKR_PROT_CLK_EN_MASK,
1238-
CDC_WSA_TX_SPKR_PROT_CLK_DISABLE);
1256+
wsa_macro_enable_disable_vi_feedback(component, false, rate_val);
12391257
break;
12401258
}
12411259

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