@@ -32,7 +32,128 @@ Groups:
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KVM_DEV_ARM_VGIC_CTRL_INIT
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request the initialization of the ITS, no additional parameter in
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kvm_device_attr.addr.
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+
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+ KVM_DEV_ARM_ITS_SAVE_TABLES
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+ save the ITS table data into guest RAM, at the location provisioned
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+ by the guest in corresponding registers/table entries.
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+
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+ The layout of the tables in guest memory defines an ABI. The entries
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+ are laid out in little endian format as described in the last paragraph.
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+
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+ KVM_DEV_ARM_ITS_RESTORE_TABLES
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+ restore the ITS tables from guest RAM to ITS internal structures.
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+
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+ The GICV3 must be restored before the ITS and all ITS registers but
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+ the GITS_CTLR must be restored before restoring the ITS tables.
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+
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+ The GITS_IIDR read-only register must also be restored before
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+ calling KVM_DEV_ARM_ITS_RESTORE_TABLES as the IIDR revision field
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+ encodes the ABI revision.
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+
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+ The expected ordering when restoring the GICv3/ITS is described in section
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+ "ITS Restore Sequence".
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+
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Errors:
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-ENXIO: ITS not properly configured as required prior to setting
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this attribute
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-ENOMEM: Memory shortage when allocating ITS internal data
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+ -EINVAL: Inconsistent restored data
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+ -EFAULT: Invalid guest ram access
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+ -EBUSY: One or more VCPUS are running
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+
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+ KVM_DEV_ARM_VGIC_GRP_ITS_REGS
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+ Attributes:
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+ The attr field of kvm_device_attr encodes the offset of the
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+ ITS register, relative to the ITS control frame base address
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+ (ITS_base).
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+
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+ kvm_device_attr.addr points to a __u64 value whatever the width
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+ of the addressed register (32/64 bits). 64 bit registers can only
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+ be accessed with full length.
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+
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+ Writes to read-only registers are ignored by the kernel except for:
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+ - GITS_CREADR. It must be restored otherwise commands in the queue
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+ will be re-executed after restoring CWRITER. GITS_CREADR must be
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+ restored before restoring the GITS_CTLR which is likely to enable the
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+ ITS. Also it must be restored after GITS_CBASER since a write to
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+ GITS_CBASER resets GITS_CREADR.
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+ - GITS_IIDR. The Revision field encodes the table layout ABI revision.
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+ In the future we might implement direct injection of virtual LPIs.
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+ This will require an upgrade of the table layout and an evolution of
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+ the ABI. GITS_IIDR must be restored before calling
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+ KVM_DEV_ARM_ITS_RESTORE_TABLES.
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+
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+ For other registers, getting or setting a register has the same
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+ effect as reading/writing the register on real hardware.
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+ Errors:
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+ -ENXIO: Offset does not correspond to any supported register
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+ -EFAULT: Invalid user pointer for attr->addr
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+ -EINVAL: Offset is not 64-bit aligned
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+ -EBUSY: one or more VCPUS are running
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+
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+ ITS Restore Sequence:
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+ -------------------------
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+
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+ The following ordering must be followed when restoring the GIC and the ITS:
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+ a) restore all guest memory and create vcpus
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+ b) restore all redistributors
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+ c) provide the its base address
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+ (KVM_DEV_ARM_VGIC_GRP_ADDR)
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+ d) restore the ITS in the following order:
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+ 1. Restore GITS_CBASER
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+ 2. Restore all other GITS_ registers, except GITS_CTLR!
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+ 3. Load the ITS table data (KVM_DEV_ARM_ITS_RESTORE_TABLES)
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+ 4. Restore GITS_CTLR
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+
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+ Then vcpus can be started.
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+
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+ ITS Table ABI REV0:
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+ -------------------
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+
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+ Revision 0 of the ABI only supports the features of a virtual GICv3, and does
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+ not support a virtual GICv4 with support for direct injection of virtual
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+ interrupts for nested hypervisors.
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+
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+ The device table and ITT are indexed by the DeviceID and EventID,
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+ respectively. The collection table is not indexed by CollectionID, and the
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+ entries in the collection are listed in no particular order.
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+ All entries are 8 bytes.
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+
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+ Device Table Entry (DTE):
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+
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+ bits: | 63| 62 ... 49 | 48 ... 5 | 4 ... 0 |
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+ values: | V | next | ITT_addr | Size |
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+
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+ where;
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+ - V indicates whether the entry is valid. If not, other fields
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+ are not meaningful.
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+ - next: equals to 0 if this entry is the last one; otherwise it
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+ corresponds to the DeviceID offset to the next DTE, capped by
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+ 2^14 -1.
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+ - ITT_addr matches bits [51:8] of the ITT address (256 Byte aligned).
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+ - Size specifies the supported number of bits for the EventID,
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+ minus one
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+
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+ Collection Table Entry (CTE):
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+
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+ bits: | 63| 62 .. 52 | 51 ... 16 | 15 ... 0 |
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+ values: | V | RES0 | RDBase | ICID |
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+
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+ where:
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+ - V indicates whether the entry is valid. If not, other fields are
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+ not meaningful.
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+ - RES0: reserved field with Should-Be-Zero-or-Preserved behavior.
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+ - RDBase is the PE number (GICR_TYPER.Processor_Number semantic),
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+ - ICID is the collection ID
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+
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+ Interrupt Translation Entry (ITE):
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+
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+ bits: | 63 ... 48 | 47 ... 16 | 15 ... 0 |
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+ values: | next | pINTID | ICID |
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+
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+ where:
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+ - next: equals to 0 if this entry is the last one; otherwise it corresponds
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+ to the EventID offset to the next ITE capped by 2^16 -1.
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+ - pINTID is the physical LPI ID; if zero, it means the entry is not valid
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+ and other fields are not meaningful.
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+ - ICID is the collection ID
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