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Merge branch 'xilinx-gmiitorgmii-converter'
Kedareswara rao Appana says: ==================== net: phy: Add xilinx gmiitorgmii converter support The Gigabit Media Independent Interface (GMII) to Reduced Gigabit Media Independent Interface (RGMII) core provides the RGMII between RGMII-compliant Ethernet physical media devices (PHY) and the Gigabit Ethernet controller. This core can be used in all three modes of operation(10/100/1000 Mb/s). The Management Data Input/Output (MDIO) interface is used to configure the Speed of operation. This core can switch dynamically between the three Different speed modes by configuring the conveter register through mdio write. The conveter sits b/w the MAC and external phy like below MACB <==> GMII2RGMII <==> RGMII_PHY MDIO <========> GMII2RGMII MCAB <=======> <========> RGMII Using MAC MDIO bus we can access both the converter and the external PHY. We need to program the line speed of the converter during run time based On the external phy negotiated speed. This patch series does the below ---> Add mask for Control register 10Mbps speed. ---> Add support for xilinx gmiitorgmii converter. ==================== Signed-off-by: David S. Miller <[email protected]>
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‎Documentation/devicetree/bindings/net/xilinx_gmii2rgmii.txt

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XILINX GMIITORGMII Converter Driver Device Tree Bindings
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--------------------------------------------------------
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The Gigabit Media Independent Interface (GMII) to Reduced Gigabit Media
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Independent Interface (RGMII) core provides the RGMII between RGMII-compliant
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Ethernet physical media devices (PHY) and the Gigabit Ethernet controller.
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This core can be used in all three modes of operation(10/100/1000 Mb/s).
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The Management Data Input/Output (MDIO) interface is used to configure the
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Speed of operation. This core can switch dynamically between the three
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Different speed modes by configuring the conveter register through mdio write.
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This converter sits between the ethernet MAC and the external phy.
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MAC <==> GMII2RGMII <==> RGMII_PHY
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For more details about mdio please refer phy.txt file in the same directory.
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Required properties:
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- compatible : Should be "xlnx,gmii-to-rgmii-1.0"
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- reg : The ID number for the phy, usually a small integer
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- phy-handle : Should point to the external phy device.
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See ethernet.txt file in the same directory.
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Example:
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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phy: ethernet-phy@0 {
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......
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};
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gmiitorgmii: gmiitorgmii@8 {
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compatible = "xlnx,gmii-to-rgmii-1.0";
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reg = <8>;
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phy-handle = <&phy>;
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};
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};

‎drivers/net/phy/Kconfig

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---help---
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Currently supports the VSC8531 and VSC8541 PHYs
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config XILINX_GMII2RGMII
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tristate "Xilinx GMII2RGMII converter driver"
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---help---
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This driver support xilinx GMII to RGMII IP core it provides
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the Reduced Gigabit Media Independent Interface(RGMII) between
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Ethernet physical media devices and the Gigabit Ethernet controller.
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endif # PHYLIB
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config MICREL_KS8995MA

‎drivers/net/phy/Makefile

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@@ -50,3 +50,4 @@ obj-$(CONFIG_MDIO_BCM_IPROC) += mdio-bcm-iproc.o
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obj-$(CONFIG_INTEL_XWAY_PHY) += intel-xway.o
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obj-$(CONFIG_MDIO_HISI_FEMAC) += mdio-hisi-femac.o
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obj-$(CONFIG_MDIO_XGENE) += mdio-xgene.o
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obj-$(CONFIG_XILINX_GMII2RGMII) += xilinx_gmii2rgmii.o

‎drivers/net/phy/xilinx_gmii2rgmii.c

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/* Xilinx GMII2RGMII Converter driver
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*
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* Copyright (C) 2016 Xilinx, Inc.
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*
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* Author: Kedareswara rao Appana <[email protected]>
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*
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* Description:
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* This driver is developed for Xilinx GMII2RGMII Converter
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/mii.h>
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#include <linux/mdio.h>
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#include <linux/phy.h>
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#include <linux/of_mdio.h>
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#define XILINX_GMII2RGMII_REG 0x10
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#define XILINX_GMII2RGMII_SPEED_MASK (BMCR_SPEED1000 | BMCR_SPEED100)
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struct gmii2rgmii {
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struct phy_device *phy_dev;
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struct phy_driver *phy_drv;
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struct phy_driver conv_phy_drv;
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int addr;
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};
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static int xgmiitorgmii_read_status(struct phy_device *phydev)
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{
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struct gmii2rgmii *priv = phydev->priv;
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u16 val = 0;
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priv->phy_drv->read_status(phydev);
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val = mdiobus_read(phydev->mdio.bus, priv->addr, XILINX_GMII2RGMII_REG);
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val &= XILINX_GMII2RGMII_SPEED_MASK;
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if (phydev->speed == SPEED_1000)
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val |= BMCR_SPEED1000;
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else if (phydev->speed == SPEED_100)
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val |= BMCR_SPEED100;
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else
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val |= BMCR_SPEED10;
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mdiobus_write(phydev->mdio.bus, priv->addr, XILINX_GMII2RGMII_REG, val);
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return 0;
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}
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int xgmiitorgmii_probe(struct mdio_device *mdiodev)
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{
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struct device *dev = &mdiodev->dev;
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struct device_node *np = dev->of_node, *phy_node;
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struct gmii2rgmii *priv;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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phy_node = of_parse_phandle(np, "phy-handle", 0);
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if (IS_ERR(phy_node)) {
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dev_err(dev, "Couldn't parse phy-handle\n");
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return -ENODEV;
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}
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priv->phy_dev = of_phy_find_device(phy_node);
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if (!priv->phy_dev) {
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dev_info(dev, "Couldn't find phydev\n");
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return -EPROBE_DEFER;
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}
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priv->addr = mdiodev->addr;
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priv->phy_drv = priv->phy_dev->drv;
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memcpy(&priv->conv_phy_drv, priv->phy_dev->drv,
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sizeof(struct phy_driver));
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priv->conv_phy_drv.read_status = xgmiitorgmii_read_status;
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priv->phy_dev->priv = priv;
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priv->phy_dev->drv = &priv->conv_phy_drv;
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return 0;
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}
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static const struct of_device_id xgmiitorgmii_of_match[] = {
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{ .compatible = "xlnx,gmii-to-rgmii-1.0" },
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{},
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};
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MODULE_DEVICE_TABLE(of, xgmiitorgmii_of_match);
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static struct mdio_driver xgmiitorgmii_driver = {
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.probe = xgmiitorgmii_probe,
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.mdiodrv.driver = {
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.name = "xgmiitorgmii",
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.of_match_table = xgmiitorgmii_of_match,
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},
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};
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mdio_module_driver(xgmiitorgmii_driver);
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MODULE_DESCRIPTION("Xilinx GMII2RGMII converter driver");
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MODULE_LICENSE("GPL");

‎include/uapi/linux/mii.h

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#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
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#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
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#define BMCR_RESET 0x8000 /* Reset to default state */
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#define BMCR_SPEED10 0x0000 /* Select 10Mbps */
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/* Basic mode status register. */
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#define BMSR_ERCAP 0x0001 /* Ext-reg capability */

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