@@ -151,11 +151,153 @@ static void ixgbe_ipsec_clear_hw_tables(struct ixgbe_adapter *adapter)
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}
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}
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+ /**
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+ * ixgbe_ipsec_stop_data
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+ * @adapter: board private structure
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+ **/
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+ static void ixgbe_ipsec_stop_data (struct ixgbe_adapter * adapter )
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+ {
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+ struct ixgbe_hw * hw = & adapter -> hw ;
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+ bool link = adapter -> link_up ;
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+ u32 t_rdy , r_rdy ;
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+ u32 limit ;
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+ u32 reg ;
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+
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+ /* halt data paths */
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+ reg = IXGBE_READ_REG (hw , IXGBE_SECTXCTRL );
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+ reg |= IXGBE_SECTXCTRL_TX_DIS ;
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+ IXGBE_WRITE_REG (hw , IXGBE_SECTXCTRL , reg );
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+
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+ reg = IXGBE_READ_REG (hw , IXGBE_SECRXCTRL );
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+ reg |= IXGBE_SECRXCTRL_RX_DIS ;
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+ IXGBE_WRITE_REG (hw , IXGBE_SECRXCTRL , reg );
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+
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+ IXGBE_WRITE_FLUSH (hw );
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+
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+ /* If the tx fifo doesn't have link, but still has data,
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+ * we can't clear the tx sec block. Set the MAC loopback
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+ * before block clear
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+ */
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+ if (!link ) {
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+ reg = IXGBE_READ_REG (hw , IXGBE_MACC );
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+ reg |= IXGBE_MACC_FLU ;
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+ IXGBE_WRITE_REG (hw , IXGBE_MACC , reg );
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+
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+ reg = IXGBE_READ_REG (hw , IXGBE_HLREG0 );
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+ reg |= IXGBE_HLREG0_LPBK ;
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+ IXGBE_WRITE_REG (hw , IXGBE_HLREG0 , reg );
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+
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+ IXGBE_WRITE_FLUSH (hw );
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+ mdelay (3 );
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+ }
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+
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+ /* wait for the paths to empty */
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+ limit = 20 ;
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+ do {
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+ mdelay (10 );
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+ t_rdy = IXGBE_READ_REG (hw , IXGBE_SECTXSTAT ) &
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+ IXGBE_SECTXSTAT_SECTX_RDY ;
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+ r_rdy = IXGBE_READ_REG (hw , IXGBE_SECRXSTAT ) &
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+ IXGBE_SECRXSTAT_SECRX_RDY ;
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+ } while (!t_rdy && !r_rdy && limit -- );
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+
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+ /* undo loopback if we played with it earlier */
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+ if (!link ) {
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+ reg = IXGBE_READ_REG (hw , IXGBE_MACC );
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+ reg &= ~IXGBE_MACC_FLU ;
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+ IXGBE_WRITE_REG (hw , IXGBE_MACC , reg );
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+
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+ reg = IXGBE_READ_REG (hw , IXGBE_HLREG0 );
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+ reg &= ~IXGBE_HLREG0_LPBK ;
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+ IXGBE_WRITE_REG (hw , IXGBE_HLREG0 , reg );
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+
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+ IXGBE_WRITE_FLUSH (hw );
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+ }
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+ }
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+
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+ /**
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+ * ixgbe_ipsec_stop_engine
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+ * @adapter: board private structure
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+ **/
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+ static void ixgbe_ipsec_stop_engine (struct ixgbe_adapter * adapter )
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+ {
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+ struct ixgbe_hw * hw = & adapter -> hw ;
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+ u32 reg ;
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+
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+ ixgbe_ipsec_stop_data (adapter );
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+
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+ /* disable Rx and Tx SA lookup */
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+ IXGBE_WRITE_REG (hw , IXGBE_IPSTXIDX , 0 );
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+ IXGBE_WRITE_REG (hw , IXGBE_IPSRXIDX , 0 );
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+
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+ /* disable the Rx and Tx engines and full packet store-n-forward */
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+ reg = IXGBE_READ_REG (hw , IXGBE_SECTXCTRL );
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+ reg |= IXGBE_SECTXCTRL_SECTX_DIS ;
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+ reg &= ~IXGBE_SECTXCTRL_STORE_FORWARD ;
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+ IXGBE_WRITE_REG (hw , IXGBE_SECTXCTRL , reg );
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+
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+ reg = IXGBE_READ_REG (hw , IXGBE_SECRXCTRL );
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+ reg |= IXGBE_SECRXCTRL_SECRX_DIS ;
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+ IXGBE_WRITE_REG (hw , IXGBE_SECRXCTRL , reg );
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+
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+ /* restore the "tx security buffer almost full threshold" to 0x250 */
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+ IXGBE_WRITE_REG (hw , IXGBE_SECTXBUFFAF , 0x250 );
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+
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+ /* Set minimum IFG between packets back to the default 0x1 */
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+ reg = IXGBE_READ_REG (hw , IXGBE_SECTXMINIFG );
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+ reg = (reg & 0xfffffff0 ) | 0x1 ;
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+ IXGBE_WRITE_REG (hw , IXGBE_SECTXMINIFG , reg );
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+
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+ /* final set for normal (no ipsec offload) processing */
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+ IXGBE_WRITE_REG (hw , IXGBE_SECTXCTRL , IXGBE_SECTXCTRL_SECTX_DIS );
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+ IXGBE_WRITE_REG (hw , IXGBE_SECRXCTRL , IXGBE_SECRXCTRL_SECRX_DIS );
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+
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+ IXGBE_WRITE_FLUSH (hw );
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+ }
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+
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+ /**
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+ * ixgbe_ipsec_start_engine
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+ * @adapter: board private structure
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+ *
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+ * NOTE: this increases power consumption whether being used or not
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+ **/
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+ static void ixgbe_ipsec_start_engine (struct ixgbe_adapter * adapter )
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+ {
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+ struct ixgbe_hw * hw = & adapter -> hw ;
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+ u32 reg ;
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+
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+ ixgbe_ipsec_stop_data (adapter );
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+
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+ /* Set minimum IFG between packets to 3 */
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+ reg = IXGBE_READ_REG (hw , IXGBE_SECTXMINIFG );
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+ reg = (reg & 0xfffffff0 ) | 0x3 ;
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+ IXGBE_WRITE_REG (hw , IXGBE_SECTXMINIFG , reg );
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+
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+ /* Set "tx security buffer almost full threshold" to 0x15 so that the
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+ * almost full indication is generated only after buffer contains at
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+ * least an entire jumbo packet.
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+ */
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+ reg = IXGBE_READ_REG (hw , IXGBE_SECTXBUFFAF );
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+ reg = (reg & 0xfffffc00 ) | 0x15 ;
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+ IXGBE_WRITE_REG (hw , IXGBE_SECTXBUFFAF , reg );
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+
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+ /* restart the data paths by clearing the DISABLE bits */
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+ IXGBE_WRITE_REG (hw , IXGBE_SECRXCTRL , 0 );
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+ IXGBE_WRITE_REG (hw , IXGBE_SECTXCTRL , IXGBE_SECTXCTRL_STORE_FORWARD );
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+
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+ /* enable Rx and Tx SA lookup */
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+ IXGBE_WRITE_REG (hw , IXGBE_IPSTXIDX , IXGBE_RXTXIDX_IPS_EN );
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+ IXGBE_WRITE_REG (hw , IXGBE_IPSRXIDX , IXGBE_RXTXIDX_IPS_EN );
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+
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+ IXGBE_WRITE_FLUSH (hw );
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+ }
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+
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/**
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* ixgbe_init_ipsec_offload - initialize security registers for IPSec operation
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* @adapter: board private structure
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**/
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void ixgbe_init_ipsec_offload (struct ixgbe_adapter * adapter )
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{
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ixgbe_ipsec_clear_hw_tables (adapter );
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+ ixgbe_ipsec_stop_engine (adapter );
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}
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