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LoongArch: Add atomic/locking headers
Add common headers (atomic, bitops, barrier and locking) for basic LoongArch support. Reviewed-by: WANG Xuerui <[email protected]> Reviewed-by: Jiaxun Yang <[email protected]> Signed-off-by: Huacai Chen <[email protected]>
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‎arch/loongarch/include/asm/atomic.h

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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Atomic operations.
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*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#ifndef _ASM_ATOMIC_H
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#define _ASM_ATOMIC_H
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#include <linux/types.h>
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#include <asm/barrier.h>
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#include <asm/cmpxchg.h>
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#include <asm/compiler.h>
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#if __SIZEOF_LONG__ == 4
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#define __LL "ll.w "
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#define __SC "sc.w "
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#define __AMADD "amadd.w "
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#define __AMAND_DB "amand_db.w "
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#define __AMOR_DB "amor_db.w "
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#define __AMXOR_DB "amxor_db.w "
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#elif __SIZEOF_LONG__ == 8
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#define __LL "ll.d "
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#define __SC "sc.d "
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#define __AMADD "amadd.d "
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#define __AMAND_DB "amand_db.d "
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#define __AMOR_DB "amor_db.d "
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#define __AMXOR_DB "amxor_db.d "
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#endif
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#define ATOMIC_INIT(i) { (i) }
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/*
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* arch_atomic_read - read atomic variable
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* @v: pointer of type atomic_t
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*
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* Atomically reads the value of @v.
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*/
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#define arch_atomic_read(v) READ_ONCE((v)->counter)
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/*
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* arch_atomic_set - set atomic variable
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* @v: pointer of type atomic_t
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* @i: required value
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*
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* Atomically sets the value of @v to @i.
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*/
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#define arch_atomic_set(v, i) WRITE_ONCE((v)->counter, (i))
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#define ATOMIC_OP(op, I, asm_op) \
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static inline void arch_atomic_##op(int i, atomic_t *v) \
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{ \
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__asm__ __volatile__( \
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"am"#asm_op"_db.w" " $zero, %1, %0 \n" \
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: "+ZB" (v->counter) \
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: "r" (I) \
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: "memory"); \
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}
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#define ATOMIC_OP_RETURN(op, I, asm_op, c_op) \
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static inline int arch_atomic_##op##_return_relaxed(int i, atomic_t *v) \
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{ \
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int result; \
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\
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__asm__ __volatile__( \
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"am"#asm_op"_db.w" " %1, %2, %0 \n" \
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: "+ZB" (v->counter), "=&r" (result) \
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: "r" (I) \
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: "memory"); \
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\
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return result c_op I; \
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}
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#define ATOMIC_FETCH_OP(op, I, asm_op) \
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static inline int arch_atomic_fetch_##op##_relaxed(int i, atomic_t *v) \
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{ \
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int result; \
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\
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__asm__ __volatile__( \
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"am"#asm_op"_db.w" " %1, %2, %0 \n" \
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: "+ZB" (v->counter), "=&r" (result) \
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: "r" (I) \
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: "memory"); \
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\
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return result; \
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}
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#define ATOMIC_OPS(op, I, asm_op, c_op) \
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ATOMIC_OP(op, I, asm_op) \
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ATOMIC_OP_RETURN(op, I, asm_op, c_op) \
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ATOMIC_FETCH_OP(op, I, asm_op)
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ATOMIC_OPS(add, i, add, +)
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ATOMIC_OPS(sub, -i, add, +)
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#define arch_atomic_add_return_relaxed arch_atomic_add_return_relaxed
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#define arch_atomic_sub_return_relaxed arch_atomic_sub_return_relaxed
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#define arch_atomic_fetch_add_relaxed arch_atomic_fetch_add_relaxed
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#define arch_atomic_fetch_sub_relaxed arch_atomic_fetch_sub_relaxed
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#undef ATOMIC_OPS
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#define ATOMIC_OPS(op, I, asm_op) \
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ATOMIC_OP(op, I, asm_op) \
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ATOMIC_FETCH_OP(op, I, asm_op)
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ATOMIC_OPS(and, i, and)
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ATOMIC_OPS(or, i, or)
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ATOMIC_OPS(xor, i, xor)
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#define arch_atomic_fetch_and_relaxed arch_atomic_fetch_and_relaxed
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#define arch_atomic_fetch_or_relaxed arch_atomic_fetch_or_relaxed
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#define arch_atomic_fetch_xor_relaxed arch_atomic_fetch_xor_relaxed
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#undef ATOMIC_OPS
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#undef ATOMIC_FETCH_OP
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#undef ATOMIC_OP_RETURN
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#undef ATOMIC_OP
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static inline int arch_atomic_fetch_add_unless(atomic_t *v, int a, int u)
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{
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int prev, rc;
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__asm__ __volatile__ (
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"0: ll.w %[p], %[c]\n"
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" beq %[p], %[u], 1f\n"
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" add.w %[rc], %[p], %[a]\n"
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" sc.w %[rc], %[c]\n"
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" beqz %[rc], 0b\n"
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" b 2f\n"
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"1:\n"
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__WEAK_LLSC_MB
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"2:\n"
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: [p]"=&r" (prev), [rc]"=&r" (rc),
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[c]"=ZB" (v->counter)
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: [a]"r" (a), [u]"r" (u)
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: "memory");
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return prev;
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}
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#define arch_atomic_fetch_add_unless arch_atomic_fetch_add_unless
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/*
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* arch_atomic_sub_if_positive - conditionally subtract integer from atomic variable
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* @i: integer value to subtract
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* @v: pointer of type atomic_t
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*
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* Atomically test @v and subtract @i if @v is greater or equal than @i.
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* The function returns the old value of @v minus @i.
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*/
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static inline int arch_atomic_sub_if_positive(int i, atomic_t *v)
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{
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int result;
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int temp;
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if (__builtin_constant_p(i)) {
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__asm__ __volatile__(
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"1: ll.w %1, %2 # atomic_sub_if_positive\n"
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" addi.w %0, %1, %3 \n"
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" or %1, %0, $zero \n"
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" blt %0, $zero, 2f \n"
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" sc.w %1, %2 \n"
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" beq $zero, %1, 1b \n"
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"2: \n"
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: "=&r" (result), "=&r" (temp),
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"+" GCC_OFF_SMALL_ASM() (v->counter)
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: "I" (-i));
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} else {
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__asm__ __volatile__(
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"1: ll.w %1, %2 # atomic_sub_if_positive\n"
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" sub.w %0, %1, %3 \n"
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" or %1, %0, $zero \n"
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" blt %0, $zero, 2f \n"
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" sc.w %1, %2 \n"
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" beq $zero, %1, 1b \n"
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"2: \n"
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: "=&r" (result), "=&r" (temp),
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"+" GCC_OFF_SMALL_ASM() (v->counter)
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: "r" (i));
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}
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return result;
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}
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#define arch_atomic_cmpxchg(v, o, n) (arch_cmpxchg(&((v)->counter), (o), (n)))
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#define arch_atomic_xchg(v, new) (arch_xchg(&((v)->counter), (new)))
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/*
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* arch_atomic_dec_if_positive - decrement by 1 if old value positive
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* @v: pointer of type atomic_t
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*/
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#define arch_atomic_dec_if_positive(v) arch_atomic_sub_if_positive(1, v)
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#ifdef CONFIG_64BIT
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#define ATOMIC64_INIT(i) { (i) }
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/*
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* arch_atomic64_read - read atomic variable
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* @v: pointer of type atomic64_t
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*
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*/
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#define arch_atomic64_read(v) READ_ONCE((v)->counter)
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/*
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* arch_atomic64_set - set atomic variable
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* @v: pointer of type atomic64_t
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* @i: required value
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*/
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#define arch_atomic64_set(v, i) WRITE_ONCE((v)->counter, (i))
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#define ATOMIC64_OP(op, I, asm_op) \
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static inline void arch_atomic64_##op(long i, atomic64_t *v) \
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{ \
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__asm__ __volatile__( \
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"am"#asm_op"_db.d " " $zero, %1, %0 \n" \
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: "+ZB" (v->counter) \
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: "r" (I) \
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: "memory"); \
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}
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#define ATOMIC64_OP_RETURN(op, I, asm_op, c_op) \
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static inline long arch_atomic64_##op##_return_relaxed(long i, atomic64_t *v) \
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{ \
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long result; \
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__asm__ __volatile__( \
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"am"#asm_op"_db.d " " %1, %2, %0 \n" \
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: "+ZB" (v->counter), "=&r" (result) \
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: "r" (I) \
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: "memory"); \
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\
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return result c_op I; \
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}
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#define ATOMIC64_FETCH_OP(op, I, asm_op) \
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static inline long arch_atomic64_fetch_##op##_relaxed(long i, atomic64_t *v) \
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{ \
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long result; \
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\
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__asm__ __volatile__( \
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"am"#asm_op"_db.d " " %1, %2, %0 \n" \
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: "+ZB" (v->counter), "=&r" (result) \
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: "r" (I) \
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: "memory"); \
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\
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return result; \
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}
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#define ATOMIC64_OPS(op, I, asm_op, c_op) \
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ATOMIC64_OP(op, I, asm_op) \
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ATOMIC64_OP_RETURN(op, I, asm_op, c_op) \
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ATOMIC64_FETCH_OP(op, I, asm_op)
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ATOMIC64_OPS(add, i, add, +)
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ATOMIC64_OPS(sub, -i, add, +)
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#define arch_atomic64_add_return_relaxed arch_atomic64_add_return_relaxed
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#define arch_atomic64_sub_return_relaxed arch_atomic64_sub_return_relaxed
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#define arch_atomic64_fetch_add_relaxed arch_atomic64_fetch_add_relaxed
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#define arch_atomic64_fetch_sub_relaxed arch_atomic64_fetch_sub_relaxed
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#undef ATOMIC64_OPS
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#define ATOMIC64_OPS(op, I, asm_op) \
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ATOMIC64_OP(op, I, asm_op) \
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ATOMIC64_FETCH_OP(op, I, asm_op)
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ATOMIC64_OPS(and, i, and)
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ATOMIC64_OPS(or, i, or)
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ATOMIC64_OPS(xor, i, xor)
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#define arch_atomic64_fetch_and_relaxed arch_atomic64_fetch_and_relaxed
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#define arch_atomic64_fetch_or_relaxed arch_atomic64_fetch_or_relaxed
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#define arch_atomic64_fetch_xor_relaxed arch_atomic64_fetch_xor_relaxed
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#undef ATOMIC64_OPS
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#undef ATOMIC64_FETCH_OP
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#undef ATOMIC64_OP_RETURN
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#undef ATOMIC64_OP
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static inline long arch_atomic64_fetch_add_unless(atomic64_t *v, long a, long u)
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{
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long prev, rc;
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__asm__ __volatile__ (
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"0: ll.d %[p], %[c]\n"
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" beq %[p], %[u], 1f\n"
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" add.d %[rc], %[p], %[a]\n"
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" sc.d %[rc], %[c]\n"
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" beqz %[rc], 0b\n"
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" b 2f\n"
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"1:\n"
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__WEAK_LLSC_MB
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"2:\n"
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: [p]"=&r" (prev), [rc]"=&r" (rc),
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[c] "=ZB" (v->counter)
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: [a]"r" (a), [u]"r" (u)
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: "memory");
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return prev;
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}
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#define arch_atomic64_fetch_add_unless arch_atomic64_fetch_add_unless
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/*
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* arch_atomic64_sub_if_positive - conditionally subtract integer from atomic variable
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* @i: integer value to subtract
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* @v: pointer of type atomic64_t
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*
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* Atomically test @v and subtract @i if @v is greater or equal than @i.
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* The function returns the old value of @v minus @i.
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*/
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static inline long arch_atomic64_sub_if_positive(long i, atomic64_t *v)
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{
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long result;
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long temp;
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if (__builtin_constant_p(i)) {
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__asm__ __volatile__(
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"1: ll.d %1, %2 # atomic64_sub_if_positive \n"
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" addi.d %0, %1, %3 \n"
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" or %1, %0, $zero \n"
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" blt %0, $zero, 2f \n"
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" sc.d %1, %2 \n"
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" beq %1, $zero, 1b \n"
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"2: \n"
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: "=&r" (result), "=&r" (temp),
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"+" GCC_OFF_SMALL_ASM() (v->counter)
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: "I" (-i));
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} else {
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__asm__ __volatile__(
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"1: ll.d %1, %2 # atomic64_sub_if_positive \n"
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" sub.d %0, %1, %3 \n"
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" or %1, %0, $zero \n"
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" blt %0, $zero, 2f \n"
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" sc.d %1, %2 \n"
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" beq %1, $zero, 1b \n"
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"2: \n"
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: "=&r" (result), "=&r" (temp),
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"+" GCC_OFF_SMALL_ASM() (v->counter)
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: "r" (i));
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}
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return result;
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}
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#define arch_atomic64_cmpxchg(v, o, n) \
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((__typeof__((v)->counter))arch_cmpxchg(&((v)->counter), (o), (n)))
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#define arch_atomic64_xchg(v, new) (arch_xchg(&((v)->counter), (new)))
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/*
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* arch_atomic64_dec_if_positive - decrement by 1 if old value positive
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* @v: pointer of type atomic64_t
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*/
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#define arch_atomic64_dec_if_positive(v) arch_atomic64_sub_if_positive(1, v)
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#endif /* CONFIG_64BIT */
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#endif /* _ASM_ATOMIC_H */

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