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Merge branch '4.14-features' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle: "This is the main pull request for 4.14 for MIPS; below a summary of the non-merge commits: CM: - Rename mips_cm_base to mips_gcr_base - Specify register size when generating accessors - Use BIT/GENMASK for register fields, order & drop shifts - Add cluster & block args to mips_cm_lock_other() CPC: - Use common CPS accessor generation macros - Use BIT/GENMASK for register fields, order & drop shifts - Introduce register modify (set/clear/change) accessors - Use change_*, set_* & clear_* where appropriate - Add CM/CPC 3.5 register definitions - Use GlobalNumber macros rather than magic numbers - Have asm/mips-cps.h include CM & CPC headers - Cluster support for topology functions - Detect CPUs in secondary clusters CPS: - Read GIC_VL_IDENT directly, not via irqchip driver DMA: - Consolidate coherent and non-coherent dma_alloc code - Don't use dma_cache_sync to implement fd_cacheflush FPU emulation / FP assist code: - Another series of 14 commits fixing corner cases such as NaN propgagation and other special input values. - Zero bits 32-63 of the result for a CLASS.D instruction. - Enhanced statics via debugfs - Do not use bools for arithmetic. GCC 7.1 moans about this. - Correct user fault_addr type Generic MIPS: - Enhancement of stack backtraces - Cleanup from non-existing options - Handle non word sized instructions when examining frame - Fix detection and decoding of ADDIUSP instruction - Fix decoding of SWSP16 instruction - Refactor handling of stack pointer in get_frame_info - Remove unreachable code from force_fcr31_sig() - Convert to using %pOF instead of full_name - Remove the R6000 support. - Move FP code from *_switch.S to *_fpu.S - Remove unused ST_OFF from r2300_switch.S - Allow platform to specify multiple its.S files - Add #includes to various files to ensure code builds reliable and without warning.. - Remove __invalidate_kernel_vmap_range - Remove plat_timer_setup - Declare various variables & functions static - Abstract CPU core & VP(E) ID access through accessor functions - Store core & VP IDs in GlobalNumber-style variable - Unify checks for sibling CPUs - Add CPU cluster number accessors - Prevent direct use of generic_defconfig - Make CONFIG_MIPS_MT_SMP default y - Add __ioread64_copy - Remove unnecessary inclusions of linux/irqchip/mips-gic.h GIC: - Introduce asm/mips-gic.h with accessor functions - Use new GIC accessor functions in mips-gic-timer - Remove counter access functions from irq-mips-gic.c - Remove gic_read_local_vp_id() from irq-mips-gic.c - Simplify shared interrupt pending/mask reads in irq-mips-gic.c - Simplify gic_local_irq_domain_map() in irq-mips-gic.c - Drop gic_(re)set_mask() functions in irq-mips-gic.c - Remove gic_set_polarity(), gic_set_trigger(), gic_set_dual_edge(), gic_map_to_pin() and gic_map_to_vpe() from irq-mips-gic.c. - Convert remaining shared reg access, local int mask access and remaining local reg access to new accessors - Move GIC_LOCAL_INT_* to asm/mips-gic.h - Remove GIC_CPU_INT* macros from irq-mips-gic.c - Move various definitions to the driver - Remove gic_get_usm_range() - Remove __gic_irq_dispatch() forward declaration - Remove gic_init() - Use mips_gic_present() in place of gic_present and remove gic_present - Move gic_get_c0_*_int() to asm/mips-gic.h - Remove linux/irqchip/mips-gic.h - Inline __gic_init() - Inline gic_basic_init() - Make pcpu_masks a per-cpu variable - Use pcpu_masks to avoid reading GIC_SH_MASK* - Clean up mti, reserved-cpu-vectors handling - Use cpumask_first_and() in gic_set_affinity() - Let the core set struct irq_common_data affinity microMIPS: - Fix microMIPS stack unwinding on big endian systems MIPS-GIC: - SYNC after enabling GIC region NUMA: - Remove the unused parent_node() macro R6: - Constify r2_decoder_tables - Add accessor & bit definitions for GlobalNumber SMP: - Constify smp ops - Allow boot_secondary SMP op to return errors VDSO: - Drop gic_get_usm_range() usage - Avoid use of linux/irqchip/mips-gic.h Platform changes: Alchemy: - Add devboard machine type to cpuinfo - update cpu feature overrides - Threaded carddetect irqs for devboards AR7: - allow NULL clock for clk_get_rate BCM63xx: - Fix ENETDMA_6345_MAXBURST_REG offset - Allow NULL clock for clk_get_rate CI20: - Enable GPIO and RTC drivers in defconfig - Add ethernet and fixed-regulator nodes to DTS Generic platform: - Move Boston and NI 169445 FIT image source to their own files - Include asm/bootinfo.h for plat_fdt_relocated() - Include asm/time.h for get_c0_*_int() - Include asm/bootinfo.h for plat_fdt_relocated() - Include asm/time.h for get_c0_*_int() - Allow filtering enabled boards by requirements - Don't explicitly disable CONFIG_USB_SUPPORT - Bump default NR_CPUS to 16 JZ4700: - Probe the jz4740-rtc driver from devicetree Lantiq: - Drop check of boot select from the spi-falcon driver. - Drop check of boot select from the lantiq-flash MTD driver. - Access boot cause register in the watchdog driver through regmap - Add device tree binding documentation for the watchdog driver - Add docs for the RCU DT bindings. - Convert the fpi bus driver to a platform_driver - Remove ltq_reset_cause() and ltq_boot_select( - Switch to a proper reset driver - Switch to a new drivers/soc GPHY driver - Add an USB PHY driver for the Lantiq SoCs using the RCU module - Use of_platform_default_populate instead of __dt_register_buses - Enable MFD_SYSCON to be able to use it for the RCU MFD - Replace ltq_boot_select() with dummy implementation. Loongson 2F: - Allow NULL clock for clk_get_rate Malta: - Use new GIC accessor functions NI 169445: - Add support for NI 169445 board. - Only include in 32r2el kernels Octeon: - Add support for watchdog of 78XX SOCs. - Add support for watchdog of CN68XX SOCs. - Expose support for mips32r1, mips32r2 and mips64r1 - Enable more drivers in config file - Add support for accessing the boot vector. - Remove old boot vector code from watchdog driver - Define watchdog registers for 70xx, 73xx, 78xx, F75xx. - Make CSR functions node aware. - Allow access to CIU3 IRQ domains. - Misc cleanups in the watchdog driver Omega2+: - New board, add support and defconfig Pistachio: - Enable Root FS on NFS in defconfig Ralink: - Add Mediatek MT7628A SoC - Allow NULL clock for clk_get_rate - Explicitly request exclusive reset control in the pci-mt7620 PCI driver. SEAD3: - Only include in 32 bit kernels by default VoCore: - Add VoCore as a vendor t0 dt-bindings - Add defconfig file" * '4.14-features' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (167 commits) MIPS: Refactor handling of stack pointer in get_frame_info MIPS: Stacktrace: Fix microMIPS stack unwinding on big endian systems MIPS: microMIPS: Fix decoding of swsp16 instruction MIPS: microMIPS: Fix decoding of addiusp instruction MIPS: microMIPS: Fix detection of addiusp instruction MIPS: Handle non word sized instructions when examining frame MIPS: ralink: allow NULL clock for clk_get_rate MIPS: Loongson 2F: allow NULL clock for clk_get_rate MIPS: BCM63XX: allow NULL clock for clk_get_rate MIPS: AR7: allow NULL clock for clk_get_rate MIPS: BCM63XX: fix ENETDMA_6345_MAXBURST_REG offset mips: Save all registers when saving the frame MIPS: Add DWARF unwinding to assembly MIPS: Make SAVE_SOME more standard MIPS: Fix issues in backtraces MIPS: jz4780: DTS: Probe the jz4740-rtc driver from devicetree MIPS: Ci20: Enable RTC driver watchdog: octeon-wdt: Add support for 78XX SOCs. watchdog: octeon-wdt: Add support for cn68XX SOCs. watchdog: octeon-wdt: File cleaning. ...
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‎Documentation/devicetree/bindings/mips/lantiq/fpi-bus.txt

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Lantiq XWAY SoC FPI BUS binding
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============================
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-------------------------------------------------------------------------------
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Required properties:
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- compatible : Should be one of
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"lantiq,xrx200-fpi"
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- reg : The address and length of the XBAR
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configuration register.
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Address and length of the FPI bus itself.
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- lantiq,rcu : A phandle to the RCU syscon
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- lantiq,offset-endianness : Offset of the endianness configuration
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register
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-------------------------------------------------------------------------------
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Example for the FPI on the xrx200 SoCs:
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fpi@10000000 {
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compatible = "lantiq,xrx200-fpi";
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ranges = <0x0 0x10000000 0xf000000>;
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reg = <0x1f400000 0x1000>,
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<0x10000000 0xf000000>;
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lantiq,rcu = <&rcu0>;
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lantiq,offset-endianness = <0x4c>;
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#address-cells = <1>;
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#size-cells = <1>;
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gptu@e100a00 {
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......
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};
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};

‎Documentation/devicetree/bindings/mips/lantiq/rcu-gphy.txt

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Lantiq XWAY SoC GPHY binding
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============================
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This binding describes a software-defined ethernet PHY, provided by the RCU
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module on newer Lantiq XWAY SoCs (xRX200 and newer).
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-------------------------------------------------------------------------------
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Required properties:
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- compatible : Should be one of
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"lantiq,xrx200a1x-gphy"
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"lantiq,xrx200a2x-gphy"
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"lantiq,xrx300-gphy"
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"lantiq,xrx330-gphy"
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- reg : Addrress of the GPHY FW load address register
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- resets : Must reference the RCU GPHY reset bit
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- reset-names : One entry, value must be "gphy" or optional "gphy2"
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- clocks : A reference to the (PMU) GPHY clock gate
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Optional properties:
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- lantiq,gphy-mode : GPHY_MODE_GE (default) or GPHY_MODE_FE as defined in
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<dt-bindings/mips/lantiq_xway_gphy.h>
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-------------------------------------------------------------------------------
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Example for the GPHys on the xRX200 SoCs:
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#include <dt-bindings/mips/lantiq_rcu_gphy.h>
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gphy0: gphy@20 {
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compatible = "lantiq,xrx200a2x-gphy";
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reg = <0x20 0x4>;
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resets = <&reset0 31 30>, <&reset1 7 7>;
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reset-names = "gphy", "gphy2";
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clocks = <&pmu0 XRX200_PMU_GATE_GPHY>;
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lantiq,gphy-mode = <GPHY_MODE_GE>;
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};

‎Documentation/devicetree/bindings/mips/lantiq/rcu.txt

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Lantiq XWAY SoC RCU binding
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===========================
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This binding describes the RCU (reset controller unit) multifunction device,
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where each sub-device has it's own set of registers.
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The RCU register range is used for multiple purposes. Mostly one device
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uses one or multiple register exclusively, but for some registers some
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bits are for one driver and some other bits are for a different driver.
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With this patch all accesses to the RCU registers will go through
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syscon.
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-------------------------------------------------------------------------------
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Required properties:
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- compatible : The first and second values must be:
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"lantiq,xrx200-rcu", "simple-mfd", "syscon"
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- reg : The address and length of the system control registers
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-------------------------------------------------------------------------------
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Example of the RCU bindings on a xRX200 SoC:
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rcu0: rcu@203000 {
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compatible = "lantiq,xrx200-rcu", "simple-mfd", "syscon";
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reg = <0x203000 0x100>;
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ranges = <0x0 0x203000 0x100>;
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big-endian;
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gphy0: gphy@20 {
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compatible = "lantiq,xrx200a2x-gphy";
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reg = <0x20 0x4>;
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resets = <&reset0 31 30>, <&reset1 7 7>;
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reset-names = "gphy", "gphy2";
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lantiq,gphy-mode = <GPHY_MODE_GE>;
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};
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gphy1: gphy@68 {
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compatible = "lantiq,xrx200a2x-gphy";
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reg = <0x68 0x4>;
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resets = <&reset0 29 28>, <&reset1 6 6>;
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reset-names = "gphy", "gphy2";
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lantiq,gphy-mode = <GPHY_MODE_GE>;
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};
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reset0: reset-controller@10 {
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compatible = "lantiq,xrx200-reset";
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reg = <0x10 4>, <0x14 4>;
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#reset-cells = <2>;
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};
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reset1: reset-controller@48 {
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compatible = "lantiq,xrx200-reset";
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reg = <0x48 4>, <0x24 4>;
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#reset-cells = <2>;
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};
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usb_phy0: usb2-phy@18 {
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compatible = "lantiq,xrx200-usb2-phy";
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reg = <0x18 4>, <0x38 4>;
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status = "disabled";
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resets = <&reset1 4 4>, <&reset0 4 4>;
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reset-names = "phy", "ctrl";
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#phy-cells = <0>;
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};
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usb_phy1: usb2-phy@34 {
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compatible = "lantiq,xrx200-usb2-phy";
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reg = <0x34 4>, <0x3C 4>;
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status = "disabled";
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resets = <&reset1 5 4>, <&reset0 4 4>;
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reset-names = "phy", "ctrl";
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#phy-cells = <0>;
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};
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reboot@10 {
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compatible = "syscon-reboot";
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reg = <0x10 4>;
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regmap = <&rcu0>;
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offset = <0x10>;
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mask = <0x40000000>;
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};
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};

‎Documentation/devicetree/bindings/mips/ni.txt

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National Instruments MIPS platforms
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required root node properties:
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- compatible: must be "ni,169445"
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CPU Nodes
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- compatible: must be "mti,mips14KEc"

‎Documentation/devicetree/bindings/mips/ralink.txt

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ralink,rt5350-soc
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ralink,mt7620a-soc
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ralink,mt7620n-soc
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ralink,mt7628a-soc

‎Documentation/devicetree/bindings/phy/phy-lantiq-rcu-usb2.txt

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Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
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===========================================
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This binding describes the USB PHY hardware provided by the RCU module on the
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Lantiq XWAY SoCs.
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This node has to be a sub node of the Lantiq RCU block.
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-------------------------------------------------------------------------------
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Required properties (controller (parent) node):
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- compatible : Should be one of
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"lantiq,ase-usb2-phy"
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"lantiq,danube-usb2-phy"
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"lantiq,xrx100-usb2-phy"
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"lantiq,xrx200-usb2-phy"
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"lantiq,xrx300-usb2-phy"
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- reg : Defines the following sets of registers in the parent
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syscon device
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- Offset of the USB PHY configuration register
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- Offset of the USB Analog configuration
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register (only for xrx200 and xrx200)
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- clocks : References to the (PMU) "phy" clk gate.
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- clock-names : Must be "phy"
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- resets : References to the RCU USB configuration reset bits.
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- reset-names : Must be one of the following:
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"phy" (optional)
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"ctrl" (shared)
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-------------------------------------------------------------------------------
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Example for the USB PHYs on an xRX200 SoC:
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usb_phy0: usb2-phy@18 {
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compatible = "lantiq,xrx200-usb2-phy";
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reg = <0x18 4>, <0x38 4>;
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clocks = <&pmu PMU_GATE_USB0_PHY>;
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clock-names = "phy";
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resets = <&reset1 4 4>, <&reset0 4 4>;
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reset-names = "phy", "ctrl";
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#phy-cells = <0>;
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};

‎Documentation/devicetree/bindings/reset/lantiq,reset.txt

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Lantiq XWAY SoC RCU reset controller binding
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============================================
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This binding describes a reset-controller found on the RCU module on Lantiq
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XWAY SoCs.
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This node has to be a sub node of the Lantiq RCU block.
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-------------------------------------------------------------------------------
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Required properties:
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- compatible : Should be one of
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"lantiq,danube-reset"
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"lantiq,xrx200-reset"
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- reg : Defines the following sets of registers in the parent
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syscon device
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- Offset of the reset set register
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- Offset of the reset status register
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- #reset-cells : Specifies the number of cells needed to encode the
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reset line, should be 2.
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The first cell takes the reset set bit and the
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second cell takes the status bit.
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-------------------------------------------------------------------------------
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Example for the reset-controllers on the xRX200 SoCs:
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reset0: reset-controller@10 {
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compatible = "lantiq,xrx200-reset";
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reg <0x10 0x04>, <0x14 0x04>;
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#reset-cells = <2>;
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};

‎Documentation/devicetree/bindings/vendor-prefixes.txt

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@@ -361,6 +361,7 @@ variscite Variscite Ltd.
361361
via VIA Technologies, Inc.
362362
virtio Virtual I/O Device Specification, developed by the OASIS consortium
363363
vivante Vivante Corporation
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vocore VoCore Studio
364365
voipac Voipac Technologies s.r.o.
365366
wd Western Digital Corp.
366367
wetek WeTek Electronics, limited.

‎Documentation/devicetree/bindings/watchdog/lantiq-wdt.txt

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Lantiq WTD watchdog binding
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============================
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This describes the binding of the Lantiq watchdog driver.
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-------------------------------------------------------------------------------
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Required properties:
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- compatible : Should be one of
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"lantiq,wdt"
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"lantiq,xrx100-wdt"
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"lantiq,xrx200-wdt", "lantiq,xrx100-wdt"
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"lantiq,falcon-wdt"
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- reg : Address of the watchdog block
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- lantiq,rcu : A phandle to the RCU syscon (required for
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"lantiq,falcon-wdt" and "lantiq,xrx100-wdt")
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-------------------------------------------------------------------------------
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Example for the watchdog on the xRX200 SoCs:
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watchdog@803f0 {
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compatible = "lantiq,xrx200-wdt", "lantiq,xrx100-wdt";
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reg = <0x803f0 0x10>;
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lantiq,rcu = <&rcu0>;
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};

‎MAINTAINERS

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@@ -7717,6 +7717,7 @@ M: John Crispin <[email protected]>
77177717
L: [email protected]
77187718
S: Maintained
77197719
F: arch/mips/lantiq
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F: drivers/soc/lantiq
77207721

77217722
LAPB module
77227723
L: [email protected]
@@ -8982,6 +8983,7 @@ M: Paul Burton <[email protected]>
89828983
L: [email protected]
89838984
S: Supported
89848985
F: arch/mips/generic/
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F: arch/mips/tools/generic-board-config.sh
89858987

89868988
MIPS/LOONGSON1 ARCHITECTURE
89878989
M: Keguang Zhang <[email protected]>
@@ -8992,6 +8994,13 @@ F: arch/mips/include/asm/mach-loongson32/
89928994
F: drivers/*/*loongson1*
89938995
F: drivers/*/*/*loongson1*
89948996

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MIPS RINT INSTRUCTION EMULATION
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M: Aleksandar Markovic <[email protected]>
8999+
L: [email protected]
9000+
S: Supported
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F: arch/mips/math-emu/sp_rint.c
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F: arch/mips/math-emu/dp_rint.c
9003+
89959004
MIROSOUND PCM20 FM RADIO RECEIVER DRIVER
89969005
M: Hans Verkuil <[email protected]>
89979006
L: [email protected]
@@ -9869,6 +9878,12 @@ F: drivers/regulator/twl-regulator.c
98699878
F: drivers/regulator/twl6030-regulator.c
98709879
F: include/linux/i2c-omap.h
98719880

9881+
ONION OMEGA2+ BOARD
9882+
M: Harvey Hunt <[email protected]>
9883+
L: [email protected]
9884+
S: Maintained
9885+
F: arch/mips/boot/dts/ralink/omega2p.dts
9886+
98729887
OMFS FILESYSTEM
98739888
M: Bob Copeland <[email protected]>
98749889
L: [email protected]
@@ -14390,6 +14405,12 @@ L: [email protected]
1439014405
S: Maintained
1439114406
F: drivers/net/vmxnet3/
1439214407

14408+
VOCORE VOCORE2 BOARD
14409+
M: Harvey Hunt <[email protected]>
14410+
L: [email protected]
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S: Maintained
14412+
F: arch/mips/boot/dts/ralink/vocore2.dts
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1439314414
VOLTAGE AND CURRENT REGULATOR FRAMEWORK
1439414415
M: Liam Girdwood <[email protected]>
1439514416
M: Mark Brown <[email protected]>

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