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Merge branch 'seville-shared-mdio'
Colin Foster says: ==================== update seville to use shared MDIO driver This patch set exposes and utilizes the shared MDIO bus in drivers/net/mdio/msio-mscc-miim.c v3: * Fix errors using uninitilized "dev" inside the probe function. * Remove phy_regmap from the setup function, since it currently isn't used * Remove GCB_PHY_PHY_CFG definition from ocelot.h - it isn't used yet... v2: * Error handling (thanks Andrew Lunn) * Fix logic errors calling mscc_miim_setup during patch 1/3 (thanks Jakub Kicinski) * Remove unnecessary felix_mdio file (thanks Vladimir Oltean) * Pass NULL to mscc_miim_setup instead of GCB_PHY_PHY_CFG, since the phy reset isn't handled at that point of the Seville driver (patch 3/3) ==================== Signed-off-by: David S. Miller <[email protected]>
2 parents 77a3124 + b996584 commit a4920d5

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4 files changed

+168
-136
lines changed

4 files changed

+168
-136
lines changed

drivers/net/dsa/ocelot/Kconfig

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@ config NET_DSA_MSCC_SEVILLE
2121
depends on NET_VENDOR_MICROSEMI
2222
depends on HAS_IOMEM
2323
depends on PTP_1588_CLOCK_OPTIONAL
24+
select MDIO_MSCC_MIIM
2425
select MSCC_OCELOT_SWITCH_LIB
2526
select NET_DSA_TAG_OCELOT_8021Q
2627
select NET_DSA_TAG_OCELOT

drivers/net/dsa/ocelot/seville_vsc9953.c

Lines changed: 10 additions & 93 deletions
Original file line numberDiff line numberDiff line change
@@ -6,18 +6,14 @@
66
#include <soc/mscc/ocelot_vcap.h>
77
#include <soc/mscc/ocelot_sys.h>
88
#include <soc/mscc/ocelot.h>
9+
#include <linux/mdio/mdio-mscc-miim.h>
10+
#include <linux/of_mdio.h>
911
#include <linux/of_platform.h>
1012
#include <linux/pcs-lynx.h>
1113
#include <linux/dsa/ocelot.h>
1214
#include <linux/iopoll.h>
1315
#include "felix.h"
1416

15-
#define MSCC_MIIM_CMD_OPR_WRITE BIT(1)
16-
#define MSCC_MIIM_CMD_OPR_READ BIT(2)
17-
#define MSCC_MIIM_CMD_WRDATA_SHIFT 4
18-
#define MSCC_MIIM_CMD_REGAD_SHIFT 20
19-
#define MSCC_MIIM_CMD_PHYAD_SHIFT 25
20-
#define MSCC_MIIM_CMD_VLD BIT(31)
2117
#define VSC9953_VCAP_POLICER_BASE 11
2218
#define VSC9953_VCAP_POLICER_MAX 31
2319
#define VSC9953_VCAP_POLICER_BASE2 120
@@ -861,7 +857,6 @@ static struct vcap_props vsc9953_vcap_props[] = {
861857
#define VSC9953_INIT_TIMEOUT 50000
862858
#define VSC9953_GCB_RST_SLEEP 100
863859
#define VSC9953_SYS_RAMINIT_SLEEP 80
864-
#define VCS9953_MII_TIMEOUT 10000
865860

866861
static int vsc9953_gcb_soft_rst_status(struct ocelot *ocelot)
867862
{
@@ -881,82 +876,6 @@ static int vsc9953_sys_ram_init_status(struct ocelot *ocelot)
881876
return val;
882877
}
883878

884-
static int vsc9953_gcb_miim_pending_status(struct ocelot *ocelot)
885-
{
886-
int val;
887-
888-
ocelot_field_read(ocelot, GCB_MIIM_MII_STATUS_PENDING, &val);
889-
890-
return val;
891-
}
892-
893-
static int vsc9953_gcb_miim_busy_status(struct ocelot *ocelot)
894-
{
895-
int val;
896-
897-
ocelot_field_read(ocelot, GCB_MIIM_MII_STATUS_BUSY, &val);
898-
899-
return val;
900-
}
901-
902-
static int vsc9953_mdio_write(struct mii_bus *bus, int phy_id, int regnum,
903-
u16 value)
904-
{
905-
struct ocelot *ocelot = bus->priv;
906-
int err, cmd, val;
907-
908-
/* Wait while MIIM controller becomes idle */
909-
err = readx_poll_timeout(vsc9953_gcb_miim_pending_status, ocelot,
910-
val, !val, 10, VCS9953_MII_TIMEOUT);
911-
if (err) {
912-
dev_err(ocelot->dev, "MDIO write: pending timeout\n");
913-
goto out;
914-
}
915-
916-
cmd = MSCC_MIIM_CMD_VLD | (phy_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
917-
(regnum << MSCC_MIIM_CMD_REGAD_SHIFT) |
918-
(value << MSCC_MIIM_CMD_WRDATA_SHIFT) |
919-
MSCC_MIIM_CMD_OPR_WRITE;
920-
921-
ocelot_write(ocelot, cmd, GCB_MIIM_MII_CMD);
922-
923-
out:
924-
return err;
925-
}
926-
927-
static int vsc9953_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
928-
{
929-
struct ocelot *ocelot = bus->priv;
930-
int err, cmd, val;
931-
932-
/* Wait until MIIM controller becomes idle */
933-
err = readx_poll_timeout(vsc9953_gcb_miim_pending_status, ocelot,
934-
val, !val, 10, VCS9953_MII_TIMEOUT);
935-
if (err) {
936-
dev_err(ocelot->dev, "MDIO read: pending timeout\n");
937-
goto out;
938-
}
939-
940-
/* Write the MIIM COMMAND register */
941-
cmd = MSCC_MIIM_CMD_VLD | (phy_id << MSCC_MIIM_CMD_PHYAD_SHIFT) |
942-
(regnum << MSCC_MIIM_CMD_REGAD_SHIFT) | MSCC_MIIM_CMD_OPR_READ;
943-
944-
ocelot_write(ocelot, cmd, GCB_MIIM_MII_CMD);
945-
946-
/* Wait while read operation via the MIIM controller is in progress */
947-
err = readx_poll_timeout(vsc9953_gcb_miim_busy_status, ocelot,
948-
val, !val, 10, VCS9953_MII_TIMEOUT);
949-
if (err) {
950-
dev_err(ocelot->dev, "MDIO read: busy timeout\n");
951-
goto out;
952-
}
953-
954-
val = ocelot_read(ocelot, GCB_MIIM_MII_DATA);
955-
956-
err = val & 0xFFFF;
957-
out:
958-
return err;
959-
}
960879

961880
/* CORE_ENA is in SYS:SYSTEM:RESET_CFG
962881
* MEM_INIT is in SYS:SYSTEM:RESET_CFG
@@ -1100,19 +1019,17 @@ static int vsc9953_mdio_bus_alloc(struct ocelot *ocelot)
11001019
return -ENOMEM;
11011020
}
11021021

1103-
bus = devm_mdiobus_alloc(dev);
1104-
if (!bus)
1105-
return -ENOMEM;
1022+
rc = mscc_miim_setup(dev, &bus, "VSC9953 internal MDIO bus",
1023+
ocelot->targets[GCB],
1024+
ocelot->map[GCB][GCB_MIIM_MII_STATUS & REG_MASK]);
11061025

1107-
bus->name = "VSC9953 internal MDIO bus";
1108-
bus->read = vsc9953_mdio_read;
1109-
bus->write = vsc9953_mdio_write;
1110-
bus->parent = dev;
1111-
bus->priv = ocelot;
1112-
snprintf(bus->id, MII_BUS_ID_SIZE, "%s-imdio", dev_name(dev));
1026+
if (rc) {
1027+
dev_err(dev, "failed to setup MDIO bus\n");
1028+
return rc;
1029+
}
11131030

11141031
/* Needed in order to initialize the bus mutex lock */
1115-
rc = mdiobus_register(bus);
1032+
rc = of_mdiobus_register(bus, NULL);
11161033
if (rc < 0) {
11171034
dev_err(dev, "failed to register MDIO bus\n");
11181035
return rc;

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