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vsyrjalavsyrjala
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drm/i915: s/get_display_clock_speed/get_cdclk/
Rename the .get_display_clock_speed() hook to .get_cdclk(). .get_cdclk() is more specific (which clock) and it's much shorter. v2: Deal with IS_GEN9_BC() v3: Deal with i945gm_get_display_clock_speed() Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Ander Conselvan de Oliveira <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
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3 files changed

+41
-62
lines changed

3 files changed

+41
-62
lines changed

‎drivers/gpu/drm/i915/i915_drv.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -602,7 +602,7 @@ struct intel_limit;
602602
struct dpll;
603603

604604
struct drm_i915_display_funcs {
605-
int (*get_display_clock_speed)(struct drm_i915_private *dev_priv);
605+
int (*get_cdclk)(struct drm_i915_private *dev_priv);
606606
int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
607607
int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
608608
int (*compute_intermediate_wm)(struct drm_device *dev,

‎drivers/gpu/drm/i915/intel_display.c

Lines changed: 39 additions & 59 deletions
Original file line numberDiff line numberDiff line change
@@ -5873,7 +5873,7 @@ static void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
58735873

58745874
static void intel_update_cdclk(struct drm_i915_private *dev_priv)
58755875
{
5876-
dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev_priv);
5876+
dev_priv->cdclk_freq = dev_priv->display.get_cdclk(dev_priv);
58775877

58785878
if (INTEL_GEN(dev_priv) >= 9)
58795879
DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz, VCO: %d kHz, ref: %d kHz\n",
@@ -6411,8 +6411,7 @@ static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
64116411
struct drm_i915_private *dev_priv = to_i915(dev);
64126412
u32 val, cmd;
64136413

6414-
WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv)
6415-
!= dev_priv->cdclk_freq);
6414+
WARN_ON(dev_priv->display.get_cdclk(dev_priv) != dev_priv->cdclk_freq);
64166415

64176416
if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
64186417
cmd = 2;
@@ -6476,8 +6475,7 @@ static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
64766475
struct drm_i915_private *dev_priv = to_i915(dev);
64776476
u32 val, cmd;
64786477

6479-
WARN_ON(dev_priv->display.get_display_clock_speed(dev_priv)
6480-
!= dev_priv->cdclk_freq);
6478+
WARN_ON(dev_priv->display.get_cdclk(dev_priv) != dev_priv->cdclk_freq);
64816479

64826480
switch (cdclk) {
64836481
case 333333:
@@ -7249,7 +7247,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
72497247
return 0;
72507248
}
72517249

7252-
static int skylake_get_display_clock_speed(struct drm_i915_private *dev_priv)
7250+
static int skylake_get_cdclk(struct drm_i915_private *dev_priv)
72537251
{
72547252
u32 cdctl;
72557253

@@ -7310,7 +7308,7 @@ static void bxt_de_pll_update(struct drm_i915_private *dev_priv)
73107308
dev_priv->cdclk_pll.ref;
73117309
}
73127310

7313-
static int broxton_get_display_clock_speed(struct drm_i915_private *dev_priv)
7311+
static int broxton_get_cdclk(struct drm_i915_private *dev_priv)
73147312
{
73157313
u32 divider;
73167314
int div, vco;
@@ -7345,7 +7343,7 @@ static int broxton_get_display_clock_speed(struct drm_i915_private *dev_priv)
73457343
return DIV_ROUND_CLOSEST(vco, div);
73467344
}
73477345

7348-
static int broadwell_get_display_clock_speed(struct drm_i915_private *dev_priv)
7346+
static int broadwell_get_cdclk(struct drm_i915_private *dev_priv)
73497347
{
73507348
uint32_t lcpll = I915_READ(LCPLL_CTL);
73517349
uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
@@ -7364,7 +7362,7 @@ static int broadwell_get_display_clock_speed(struct drm_i915_private *dev_priv)
73647362
return 675000;
73657363
}
73667364

7367-
static int haswell_get_display_clock_speed(struct drm_i915_private *dev_priv)
7365+
static int haswell_get_cdclk(struct drm_i915_private *dev_priv)
73687366
{
73697367
uint32_t lcpll = I915_READ(LCPLL_CTL);
73707368
uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
@@ -7381,23 +7379,23 @@ static int haswell_get_display_clock_speed(struct drm_i915_private *dev_priv)
73817379
return 540000;
73827380
}
73837381

7384-
static int valleyview_get_display_clock_speed(struct drm_i915_private *dev_priv)
7382+
static int valleyview_get_cdclk(struct drm_i915_private *dev_priv)
73857383
{
73867384
return vlv_get_cck_clock_hpll(dev_priv, "cdclk",
73877385
CCK_DISPLAY_CLOCK_CONTROL);
73887386
}
73897387

7390-
static int ilk_get_display_clock_speed(struct drm_i915_private *dev_priv)
7388+
static int ilk_get_cdclk(struct drm_i915_private *dev_priv)
73917389
{
73927390
return 450000;
73937391
}
73947392

7395-
static int i945_get_display_clock_speed(struct drm_i915_private *dev_priv)
7393+
static int i945_get_cdclk(struct drm_i915_private *dev_priv)
73967394
{
73977395
return 400000;
73987396
}
73997397

7400-
static int i945gm_get_display_clock_speed(struct drm_i915_private *dev_priv)
7398+
static int i945gm_get_cdclk(struct drm_i915_private *dev_priv)
74017399
{
74027400
struct pci_dev *pdev = dev_priv->drm.pdev;
74037401
u16 gcfgc = 0;
@@ -7417,17 +7415,17 @@ static int i945gm_get_display_clock_speed(struct drm_i915_private *dev_priv)
74177415
}
74187416
}
74197417

7420-
static int i915_get_display_clock_speed(struct drm_i915_private *dev_priv)
7418+
static int i915_get_cdclk(struct drm_i915_private *dev_priv)
74217419
{
74227420
return 333333;
74237421
}
74247422

7425-
static int i9xx_misc_get_display_clock_speed(struct drm_i915_private *dev_priv)
7423+
static int i9xx_misc_get_cdclk(struct drm_i915_private *dev_priv)
74267424
{
74277425
return 200000;
74287426
}
74297427

7430-
static int pnv_get_display_clock_speed(struct drm_i915_private *dev_priv)
7428+
static int pnv_get_cdclk(struct drm_i915_private *dev_priv)
74317429
{
74327430
struct pci_dev *pdev = dev_priv->drm.pdev;
74337431
u16 gcfgc = 0;
@@ -7452,7 +7450,7 @@ static int pnv_get_display_clock_speed(struct drm_i915_private *dev_priv)
74527450
}
74537451
}
74547452

7455-
static int i915gm_get_display_clock_speed(struct drm_i915_private *dev_priv)
7453+
static int i915gm_get_cdclk(struct drm_i915_private *dev_priv)
74567454
{
74577455
struct pci_dev *pdev = dev_priv->drm.pdev;
74587456
u16 gcfgc = 0;
@@ -7472,12 +7470,12 @@ static int i915gm_get_display_clock_speed(struct drm_i915_private *dev_priv)
74727470
}
74737471
}
74747472

7475-
static int i865_get_display_clock_speed(struct drm_i915_private *dev_priv)
7473+
static int i865_get_cdclk(struct drm_i915_private *dev_priv)
74767474
{
74777475
return 266667;
74787476
}
74797477

7480-
static int i85x_get_display_clock_speed(struct drm_i915_private *dev_priv)
7478+
static int i85x_get_cdclk(struct drm_i915_private *dev_priv)
74817479
{
74827480
struct pci_dev *pdev = dev_priv->drm.pdev;
74837481
u16 hpllcc = 0;
@@ -7515,7 +7513,7 @@ static int i85x_get_display_clock_speed(struct drm_i915_private *dev_priv)
75157513
return 0;
75167514
}
75177515

7518-
static int i830_get_display_clock_speed(struct drm_i915_private *dev_priv)
7516+
static int i830_get_cdclk(struct drm_i915_private *dev_priv)
75197517
{
75207518
return 133333;
75217519
}
@@ -7588,7 +7586,7 @@ static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
75887586
return vco;
75897587
}
75907588

7591-
static int gm45_get_display_clock_speed(struct drm_i915_private *dev_priv)
7589+
static int gm45_get_cdclk(struct drm_i915_private *dev_priv)
75927590
{
75937591
struct pci_dev *pdev = dev_priv->drm.pdev;
75947592
unsigned int cdclk_sel, vco = intel_hpll_vco(dev_priv);
@@ -7611,7 +7609,7 @@ static int gm45_get_display_clock_speed(struct drm_i915_private *dev_priv)
76117609
}
76127610
}
76137611

7614-
static int i965gm_get_display_clock_speed(struct drm_i915_private *dev_priv)
7612+
static int i965gm_get_cdclk(struct drm_i915_private *dev_priv)
76157613
{
76167614
struct pci_dev *pdev = dev_priv->drm.pdev;
76177615
static const uint8_t div_3200[] = { 16, 10, 8 };
@@ -7649,7 +7647,7 @@ static int i965gm_get_display_clock_speed(struct drm_i915_private *dev_priv)
76497647
return 200000;
76507648
}
76517649

7652-
static int g33_get_display_clock_speed(struct drm_i915_private *dev_priv)
7650+
static int g33_get_cdclk(struct drm_i915_private *dev_priv)
76537651
{
76547652
struct pci_dev *pdev = dev_priv->drm.pdev;
76557653
static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
@@ -16242,61 +16240,43 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
1624216240

1624316241
/* Returns the core display clock speed */
1624416242
if (IS_GEN9_BC(dev_priv))
16245-
dev_priv->display.get_display_clock_speed =
16246-
skylake_get_display_clock_speed;
16243+
dev_priv->display.get_cdclk = skylake_get_cdclk;
1624716244
else if (IS_GEN9_LP(dev_priv))
16248-
dev_priv->display.get_display_clock_speed =
16249-
broxton_get_display_clock_speed;
16245+
dev_priv->display.get_cdclk = broxton_get_cdclk;
1625016246
else if (IS_BROADWELL(dev_priv))
16251-
dev_priv->display.get_display_clock_speed =
16252-
broadwell_get_display_clock_speed;
16247+
dev_priv->display.get_cdclk = broadwell_get_cdclk;
1625316248
else if (IS_HASWELL(dev_priv))
16254-
dev_priv->display.get_display_clock_speed =
16255-
haswell_get_display_clock_speed;
16249+
dev_priv->display.get_cdclk = haswell_get_cdclk;
1625616250
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
16257-
dev_priv->display.get_display_clock_speed =
16258-
valleyview_get_display_clock_speed;
16251+
dev_priv->display.get_cdclk = valleyview_get_cdclk;
1625916252
else if (IS_GEN5(dev_priv))
16260-
dev_priv->display.get_display_clock_speed =
16261-
ilk_get_display_clock_speed;
16253+
dev_priv->display.get_cdclk = ilk_get_cdclk;
1626216254
else if (IS_I945G(dev_priv) || IS_I965G(dev_priv) ||
1626316255
IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
16264-
dev_priv->display.get_display_clock_speed =
16265-
i945_get_display_clock_speed;
16256+
dev_priv->display.get_cdclk = i945_get_cdclk;
1626616257
else if (IS_GM45(dev_priv))
16267-
dev_priv->display.get_display_clock_speed =
16268-
gm45_get_display_clock_speed;
16258+
dev_priv->display.get_cdclk = gm45_get_cdclk;
1626916259
else if (IS_I965GM(dev_priv))
16270-
dev_priv->display.get_display_clock_speed =
16271-
i965gm_get_display_clock_speed;
16260+
dev_priv->display.get_cdclk = i965gm_get_cdclk;
1627216261
else if (IS_PINEVIEW(dev_priv))
16273-
dev_priv->display.get_display_clock_speed =
16274-
pnv_get_display_clock_speed;
16262+
dev_priv->display.get_cdclk = pnv_get_cdclk;
1627516263
else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
16276-
dev_priv->display.get_display_clock_speed =
16277-
g33_get_display_clock_speed;
16264+
dev_priv->display.get_cdclk = g33_get_cdclk;
1627816265
else if (IS_I915G(dev_priv))
16279-
dev_priv->display.get_display_clock_speed =
16280-
i915_get_display_clock_speed;
16266+
dev_priv->display.get_cdclk = i915_get_cdclk;
1628116267
else if (IS_I845G(dev_priv))
16282-
dev_priv->display.get_display_clock_speed =
16283-
i9xx_misc_get_display_clock_speed;
16268+
dev_priv->display.get_cdclk = i9xx_misc_get_cdclk;
1628416269
else if (IS_I945GM(dev_priv))
16285-
dev_priv->display.get_display_clock_speed =
16286-
i945gm_get_display_clock_speed;
16270+
dev_priv->display.get_cdclk = i945gm_get_cdclk;
1628716271
else if (IS_I915GM(dev_priv))
16288-
dev_priv->display.get_display_clock_speed =
16289-
i915gm_get_display_clock_speed;
16272+
dev_priv->display.get_cdclk = i915gm_get_cdclk;
1629016273
else if (IS_I865G(dev_priv))
16291-
dev_priv->display.get_display_clock_speed =
16292-
i865_get_display_clock_speed;
16274+
dev_priv->display.get_cdclk = i865_get_cdclk;
1629316275
else if (IS_I85X(dev_priv))
16294-
dev_priv->display.get_display_clock_speed =
16295-
i85x_get_display_clock_speed;
16276+
dev_priv->display.get_cdclk = i85x_get_cdclk;
1629616277
else { /* 830 */
1629716278
WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
16298-
dev_priv->display.get_display_clock_speed =
16299-
i830_get_display_clock_speed;
16279+
dev_priv->display.get_cdclk = i830_get_cdclk;
1630016280
}
1630116281

1630216282
if (IS_GEN5(dev_priv)) {

‎drivers/gpu/drm/i915/intel_runtime_pm.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -966,8 +966,7 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
966966
{
967967
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
968968

969-
WARN_ON(dev_priv->cdclk_freq !=
970-
dev_priv->display.get_display_clock_speed(dev_priv));
969+
WARN_ON(dev_priv->cdclk_freq != dev_priv->display.get_cdclk(dev_priv));
971970

972971
gen9_assert_dbuf_enabled(dev_priv);
973972

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