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Disintegrate asm/system.h for Alpha
Disintegrate asm/system.h for Alpha. Signed-off-by: David Howells <[email protected]> cc: [email protected]
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+388
-402
lines changed

‎arch/alpha/boot/bootp.c

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@@ -13,7 +13,6 @@
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#include <generated/utsrelease.h>
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#include <linux/mm.h>
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16-
#include <asm/system.h>
1716
#include <asm/console.h>
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#include <asm/hwrpb.h>
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#include <asm/pgtable.h>

‎arch/alpha/boot/bootpz.c

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@@ -15,7 +15,6 @@
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#include <generated/utsrelease.h>
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#include <linux/mm.h>
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18-
#include <asm/system.h>
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#include <asm/console.h>
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#include <asm/hwrpb.h>
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#include <asm/pgtable.h>

‎arch/alpha/boot/head.S

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@@ -4,7 +4,6 @@
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* initial bootloader stuff..
55
*/
66

7-
#include <asm/system.h>
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.set noreorder
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.globl __start

‎arch/alpha/boot/main.c

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#include <generated/utsrelease.h>
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#include <linux/mm.h>
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#include <asm/system.h>
1514
#include <asm/console.h>
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#include <asm/hwrpb.h>
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#include <asm/pgtable.h>

‎arch/alpha/include/asm/atomic.h

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@@ -3,7 +3,6 @@
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44
#include <linux/types.h>
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#include <asm/barrier.h>
6-
#include <asm/system.h>
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87
/*
98
* Atomic operations that C can't guarantee us. Useful for
@@ -169,6 +168,73 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
169168
return result;
170169
}
171170

171+
/*
172+
* Atomic exchange routines.
173+
*/
174+
175+
#define __ASM__MB
176+
#define ____xchg(type, args...) __xchg ## type ## _local(args)
177+
#define ____cmpxchg(type, args...) __cmpxchg ## type ## _local(args)
178+
#include <asm/xchg.h>
179+
180+
#define xchg_local(ptr,x) \
181+
({ \
182+
__typeof__(*(ptr)) _x_ = (x); \
183+
(__typeof__(*(ptr))) __xchg_local((ptr), (unsigned long)_x_, \
184+
sizeof(*(ptr))); \
185+
})
186+
187+
#define cmpxchg_local(ptr, o, n) \
188+
({ \
189+
__typeof__(*(ptr)) _o_ = (o); \
190+
__typeof__(*(ptr)) _n_ = (n); \
191+
(__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_, \
192+
(unsigned long)_n_, \
193+
sizeof(*(ptr))); \
194+
})
195+
196+
#define cmpxchg64_local(ptr, o, n) \
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({ \
198+
BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
199+
cmpxchg_local((ptr), (o), (n)); \
200+
})
201+
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#ifdef CONFIG_SMP
203+
#undef __ASM__MB
204+
#define __ASM__MB "\tmb\n"
205+
#endif
206+
#undef ____xchg
207+
#undef ____cmpxchg
208+
#define ____xchg(type, args...) __xchg ##type(args)
209+
#define ____cmpxchg(type, args...) __cmpxchg ##type(args)
210+
#include <asm/xchg.h>
211+
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#define xchg(ptr,x) \
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({ \
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__typeof__(*(ptr)) _x_ = (x); \
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(__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, \
216+
sizeof(*(ptr))); \
217+
})
218+
219+
#define cmpxchg(ptr, o, n) \
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({ \
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__typeof__(*(ptr)) _o_ = (o); \
222+
__typeof__(*(ptr)) _n_ = (n); \
223+
(__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
224+
(unsigned long)_n_, sizeof(*(ptr)));\
225+
})
226+
227+
#define cmpxchg64(ptr, o, n) \
228+
({ \
229+
BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
230+
cmpxchg((ptr), (o), (n)); \
231+
})
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#undef __ASM__MB
234+
#undef ____cmpxchg
235+
236+
#define __HAVE_ARCH_CMPXCHG 1
237+
172238
#define atomic64_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
173239
#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
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‎arch/alpha/include/asm/auxvec.h

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#define AT_L2_CACHESHAPE 36
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#define AT_L3_CACHESHAPE 37
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24+
#define AT_VECTOR_SIZE_ARCH 4 /* entries in ARCH_DLINFO */
25+
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#endif /* __ASM_ALPHA_AUXVEC_H */

‎arch/alpha/include/asm/core_lca.h

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@@ -1,8 +1,8 @@
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#ifndef __ALPHA_LCA__H__
22
#define __ALPHA_LCA__H__
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4-
#include <asm/system.h>
54
#include <asm/compiler.h>
5+
#include <asm/mce.h>
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77
/*
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* Low Cost Alpha (LCA) definitions (these apply to 21066 and 21068,

‎arch/alpha/include/asm/core_mcpcia.h

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#include <linux/types.h>
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#include <asm/compiler.h>
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#include <asm/mce.h>
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/*
1213
* MCPCIA is the internal name for a core logic chipset which provides

‎arch/alpha/include/asm/core_t2.h

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#include <linux/types.h>
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#include <linux/spinlock.h>
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#include <asm/compiler.h>
10-
#include <asm/system.h>
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/*
1312
* T2 is the internal name for the core logic chipset which provides

‎arch/alpha/include/asm/elf.h

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#define __ASM_ALPHA_ELF_H
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44
#include <asm/auxvec.h>
5+
#include <asm/special_insns.h>
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67
/* Special values for the st_other field in the symbol table. */
78

‎arch/alpha/include/asm/exec.h

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#ifndef __ALPHA_EXEC_H
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#define __ALPHA_EXEC_H
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4+
#define arch_align_stack(x) (x)
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#endif /* __ALPHA_EXEC_H */

‎arch/alpha/include/asm/fpu.h

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#ifndef __ASM_ALPHA_FPU_H
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#define __ASM_ALPHA_FPU_H
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4+
#include <asm/special_insns.h>
5+
46
/*
57
* Alpha floating-point control register defines:
68
*/

‎arch/alpha/include/asm/io.h

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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <asm/compiler.h>
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#include <asm/system.h>
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#include <asm/pgtable.h>
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#include <asm/machvec.h>
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#include <asm/hwrpb.h>

‎arch/alpha/include/asm/irqflags.h

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#ifndef __ALPHA_IRQFLAGS_H
22
#define __ALPHA_IRQFLAGS_H
33

4-
#include <asm/system.h>
4+
#include <asm/pal.h>
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66
#define IPL_MIN 0
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#define IPL_SW0 1

‎arch/alpha/include/asm/mce.h

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#ifndef __ALPHA_MCE_H
2+
#define __ALPHA_MCE_H
3+
4+
/*
5+
* This is the logout header that should be common to all platforms
6+
* (assuming they are running OSF/1 PALcode, I guess).
7+
*/
8+
struct el_common {
9+
unsigned int size; /* size in bytes of logout area */
10+
unsigned int sbz1 : 30; /* should be zero */
11+
unsigned int err2 : 1; /* second error */
12+
unsigned int retry : 1; /* retry flag */
13+
unsigned int proc_offset; /* processor-specific offset */
14+
unsigned int sys_offset; /* system-specific offset */
15+
unsigned int code; /* machine check code */
16+
unsigned int frame_rev; /* frame revision */
17+
};
18+
19+
/* Machine Check Frame for uncorrectable errors (Large format)
20+
* --- This is used to log uncorrectable errors such as
21+
* double bit ECC errors.
22+
* --- These errors are detected by both processor and systems.
23+
*/
24+
struct el_common_EV5_uncorrectable_mcheck {
25+
unsigned long shadow[8]; /* Shadow reg. 8-14, 25 */
26+
unsigned long paltemp[24]; /* PAL TEMP REGS. */
27+
unsigned long exc_addr; /* Address of excepting instruction*/
28+
unsigned long exc_sum; /* Summary of arithmetic traps. */
29+
unsigned long exc_mask; /* Exception mask (from exc_sum). */
30+
unsigned long pal_base; /* Base address for PALcode. */
31+
unsigned long isr; /* Interrupt Status Reg. */
32+
unsigned long icsr; /* CURRENT SETUP OF EV5 IBOX */
33+
unsigned long ic_perr_stat; /* I-CACHE Reg. <11> set Data parity
34+
<12> set TAG parity*/
35+
unsigned long dc_perr_stat; /* D-CACHE error Reg. Bits set to 1:
36+
<2> Data error in bank 0
37+
<3> Data error in bank 1
38+
<4> Tag error in bank 0
39+
<5> Tag error in bank 1 */
40+
unsigned long va; /* Effective VA of fault or miss. */
41+
unsigned long mm_stat; /* Holds the reason for D-stream
42+
fault or D-cache parity errors */
43+
unsigned long sc_addr; /* Address that was being accessed
44+
when EV5 detected Secondary cache
45+
failure. */
46+
unsigned long sc_stat; /* Helps determine if the error was
47+
TAG/Data parity(Secondary Cache)*/
48+
unsigned long bc_tag_addr; /* Contents of EV5 BC_TAG_ADDR */
49+
unsigned long ei_addr; /* Physical address of any transfer
50+
that is logged in EV5 EI_STAT */
51+
unsigned long fill_syndrome; /* For correcting ECC errors. */
52+
unsigned long ei_stat; /* Helps identify reason of any
53+
processor uncorrectable error
54+
at its external interface. */
55+
unsigned long ld_lock; /* Contents of EV5 LD_LOCK register*/
56+
};
57+
58+
struct el_common_EV6_mcheck {
59+
unsigned int FrameSize; /* Bytes, including this field */
60+
unsigned int FrameFlags; /* <31> = Retry, <30> = Second Error */
61+
unsigned int CpuOffset; /* Offset to CPU-specific info */
62+
unsigned int SystemOffset; /* Offset to system-specific info */
63+
unsigned int MCHK_Code;
64+
unsigned int MCHK_Frame_Rev;
65+
unsigned long I_STAT; /* EV6 Internal Processor Registers */
66+
unsigned long DC_STAT; /* (See the 21264 Spec) */
67+
unsigned long C_ADDR;
68+
unsigned long DC1_SYNDROME;
69+
unsigned long DC0_SYNDROME;
70+
unsigned long C_STAT;
71+
unsigned long C_STS;
72+
unsigned long MM_STAT;
73+
unsigned long EXC_ADDR;
74+
unsigned long IER_CM;
75+
unsigned long ISUM;
76+
unsigned long RESERVED0;
77+
unsigned long PAL_BASE;
78+
unsigned long I_CTL;
79+
unsigned long PCTX;
80+
};
81+
82+
83+
#endif /* __ALPHA_MCE_H */

‎arch/alpha/include/asm/mmu_context.h

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* Copyright (C) 1996, Linus Torvalds
88
*/
99

10-
#include <asm/system.h>
1110
#include <asm/machvec.h>
1211
#include <asm/compiler.h>
1312
#include <asm-generic/mm_hooks.h>

‎arch/alpha/include/asm/pal.h

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#define PAL_retsys 61
4949
#define PAL_rti 63
5050

51+
#ifdef __KERNEL__
52+
#ifndef __ASSEMBLY__
53+
54+
extern void halt(void) __attribute__((noreturn));
55+
#define __halt() __asm__ __volatile__ ("call_pal %0 #halt" : : "i" (PAL_halt))
56+
57+
#define imb() \
58+
__asm__ __volatile__ ("call_pal %0 #imb" : : "i" (PAL_imb) : "memory")
59+
60+
#define draina() \
61+
__asm__ __volatile__ ("call_pal %0 #draina" : : "i" (PAL_draina) : "memory")
62+
63+
#define __CALL_PAL_R0(NAME, TYPE) \
64+
extern inline TYPE NAME(void) \
65+
{ \
66+
register TYPE __r0 __asm__("$0"); \
67+
__asm__ __volatile__( \
68+
"call_pal %1 # " #NAME \
69+
:"=r" (__r0) \
70+
:"i" (PAL_ ## NAME) \
71+
:"$1", "$16", "$22", "$23", "$24", "$25"); \
72+
return __r0; \
73+
}
74+
75+
#define __CALL_PAL_W1(NAME, TYPE0) \
76+
extern inline void NAME(TYPE0 arg0) \
77+
{ \
78+
register TYPE0 __r16 __asm__("$16") = arg0; \
79+
__asm__ __volatile__( \
80+
"call_pal %1 # "#NAME \
81+
: "=r"(__r16) \
82+
: "i"(PAL_ ## NAME), "0"(__r16) \
83+
: "$1", "$22", "$23", "$24", "$25"); \
84+
}
85+
86+
#define __CALL_PAL_W2(NAME, TYPE0, TYPE1) \
87+
extern inline void NAME(TYPE0 arg0, TYPE1 arg1) \
88+
{ \
89+
register TYPE0 __r16 __asm__("$16") = arg0; \
90+
register TYPE1 __r17 __asm__("$17") = arg1; \
91+
__asm__ __volatile__( \
92+
"call_pal %2 # "#NAME \
93+
: "=r"(__r16), "=r"(__r17) \
94+
: "i"(PAL_ ## NAME), "0"(__r16), "1"(__r17) \
95+
: "$1", "$22", "$23", "$24", "$25"); \
96+
}
97+
98+
#define __CALL_PAL_RW1(NAME, RTYPE, TYPE0) \
99+
extern inline RTYPE NAME(TYPE0 arg0) \
100+
{ \
101+
register RTYPE __r0 __asm__("$0"); \
102+
register TYPE0 __r16 __asm__("$16") = arg0; \
103+
__asm__ __volatile__( \
104+
"call_pal %2 # "#NAME \
105+
: "=r"(__r16), "=r"(__r0) \
106+
: "i"(PAL_ ## NAME), "0"(__r16) \
107+
: "$1", "$22", "$23", "$24", "$25"); \
108+
return __r0; \
109+
}
110+
111+
#define __CALL_PAL_RW2(NAME, RTYPE, TYPE0, TYPE1) \
112+
extern inline RTYPE NAME(TYPE0 arg0, TYPE1 arg1) \
113+
{ \
114+
register RTYPE __r0 __asm__("$0"); \
115+
register TYPE0 __r16 __asm__("$16") = arg0; \
116+
register TYPE1 __r17 __asm__("$17") = arg1; \
117+
__asm__ __volatile__( \
118+
"call_pal %3 # "#NAME \
119+
: "=r"(__r16), "=r"(__r17), "=r"(__r0) \
120+
: "i"(PAL_ ## NAME), "0"(__r16), "1"(__r17) \
121+
: "$1", "$22", "$23", "$24", "$25"); \
122+
return __r0; \
123+
}
124+
125+
__CALL_PAL_W1(cflush, unsigned long);
126+
__CALL_PAL_R0(rdmces, unsigned long);
127+
__CALL_PAL_R0(rdps, unsigned long);
128+
__CALL_PAL_R0(rdusp, unsigned long);
129+
__CALL_PAL_RW1(swpipl, unsigned long, unsigned long);
130+
__CALL_PAL_R0(whami, unsigned long);
131+
__CALL_PAL_W2(wrent, void*, unsigned long);
132+
__CALL_PAL_W1(wripir, unsigned long);
133+
__CALL_PAL_W1(wrkgp, unsigned long);
134+
__CALL_PAL_W1(wrmces, unsigned long);
135+
__CALL_PAL_RW2(wrperfmon, unsigned long, unsigned long, unsigned long);
136+
__CALL_PAL_W1(wrusp, unsigned long);
137+
__CALL_PAL_W1(wrvptptr, unsigned long);
138+
139+
/*
140+
* TB routines..
141+
*/
142+
#define __tbi(nr,arg,arg1...) \
143+
({ \
144+
register unsigned long __r16 __asm__("$16") = (nr); \
145+
register unsigned long __r17 __asm__("$17"); arg; \
146+
__asm__ __volatile__( \
147+
"call_pal %3 #__tbi" \
148+
:"=r" (__r16),"=r" (__r17) \
149+
:"0" (__r16),"i" (PAL_tbi) ,##arg1 \
150+
:"$0", "$1", "$22", "$23", "$24", "$25"); \
151+
})
152+
153+
#define tbi(x,y) __tbi(x,__r17=(y),"1" (__r17))
154+
#define tbisi(x) __tbi(1,__r17=(x),"1" (__r17))
155+
#define tbisd(x) __tbi(2,__r17=(x),"1" (__r17))
156+
#define tbis(x) __tbi(3,__r17=(x),"1" (__r17))
157+
#define tbiap() __tbi(-1, /* no second argument */)
158+
#define tbia() __tbi(-2, /* no second argument */)
159+
160+
#endif /* !__ASSEMBLY__ */
161+
#endif /* __KERNEL__ */
162+
51163
#endif /* __ALPHA_PAL_H */

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