Skip to content

Commit f1b744f

Browse files
committed
Merge tag 'riscv-for-linus-5.17-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V updates from Palmer Dabbelt: - Support for the DA9063 as used on the HiFive Unmatched. - Support for relative extables, which puts us in line with other architectures and save some space in vmlinux. - A handful of kexec fixes/improvements, including the ability to run crash kernels from PCI-addressable memory on the HiFive Unmatched. - Support for the SBI SRST extension, which allows systems that do not have an explicit driver in Linux to reboot. - A handful of fixes and cleanups, including to the defconfigs and device trees. * tag 'riscv-for-linus-5.17-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (52 commits) RISC-V: Use SBI SRST extension when available riscv: mm: fix wrong phys_ram_base value for RV64 RISC-V: Use common riscv_cpuid_to_hartid_mask() for both SMP=y and SMP=n riscv: head: remove useless __PAGE_ALIGNED_BSS and .balign riscv: errata: alternative: mark vendor_patch_func __initdata riscv: head: make secondary_start_common() static riscv: remove cpu_stop() riscv: try to allocate crashkern region from 32bit addressible memory riscv: use hart id instead of cpu id on machine_kexec riscv: Don't use va_pa_offset on kdump riscv: dts: sifive: fu540-c000: Fix PLIC node riscv: dts: sifive: fu540-c000: Drop bogus soc node compatible values riscv: dts: sifive: Group tuples in register properties riscv: dts: sifive: Group tuples in interrupt properties riscv: dts: microchip: mpfs: Group tuples in interrupt properties riscv: dts: microchip: mpfs: Fix clock controller node riscv: dts: microchip: mpfs: Fix reference clock node riscv: dts: microchip: mpfs: Fix PLIC node riscv: dts: microchip: mpfs: Drop empty chosen node riscv: dts: canaan: Group tuples in interrupt properties ...
2 parents fd6f57b + b579dfe commit f1b744f

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

42 files changed

+512
-392
lines changed

arch/riscv/Kconfig

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,7 @@ config RISCV
1414
def_bool y
1515
select ARCH_CLOCKSOURCE_INIT
1616
select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION
17+
select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2
1718
select ARCH_HAS_BINFMT_FLAT
1819
select ARCH_HAS_DEBUG_VM_PGTABLE
1920
select ARCH_HAS_DEBUG_VIRTUAL if MMU
@@ -75,6 +76,7 @@ config RISCV
7576
select HAVE_ARCH_SECCOMP_FILTER
7677
select HAVE_ARCH_TRACEHOOK
7778
select HAVE_ARCH_TRANSPARENT_HUGEPAGE if 64BIT && MMU
79+
select ARCH_ENABLE_THP_MIGRATION if TRANSPARENT_HUGEPAGE
7880
select HAVE_ARCH_THREAD_STRUCT_WHITELIST
7981
select HAVE_ARCH_VMAP_STACK if MMU && 64BIT
8082
select HAVE_ASM_MODVERSIONS
@@ -279,7 +281,7 @@ choice
279281
depends on 32BIT
280282
bool "1GiB"
281283
config MAXPHYSMEM_2GB
282-
depends on 64BIT && CMODEL_MEDLOW
284+
depends on 64BIT
283285
bool "2GiB"
284286
config MAXPHYSMEM_128GB
285287
depends on 64BIT && CMODEL_MEDANY

arch/riscv/boot/dts/canaan/k210.dtsi

Lines changed: 12 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -103,8 +103,8 @@
103103
clint0: timer@2000000 {
104104
compatible = "canaan,k210-clint", "sifive,clint0";
105105
reg = <0x2000000 0xC000>;
106-
interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
107-
&cpu1_intc 3 &cpu1_intc 7>;
106+
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
107+
<&cpu1_intc 3>, <&cpu1_intc 7>;
108108
};
109109

110110
plic0: interrupt-controller@c000000 {
@@ -113,7 +113,7 @@
113113
compatible = "canaan,k210-plic", "sifive,plic-1.0.0";
114114
reg = <0xC000000 0x4000000>;
115115
interrupt-controller;
116-
interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11>;
116+
interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>;
117117
riscv,ndev = <65>;
118118
};
119119

@@ -130,18 +130,19 @@
130130
compatible = "canaan,k210-gpiohs", "sifive,gpio0";
131131
reg = <0x38001000 0x1000>;
132132
interrupt-controller;
133-
interrupts = <34 35 36 37 38 39 40 41
134-
42 43 44 45 46 47 48 49
135-
50 51 52 53 54 55 56 57
136-
58 59 60 61 62 63 64 65>;
133+
interrupts = <34>, <35>, <36>, <37>, <38>, <39>, <40>,
134+
<41>, <42>, <43>, <44>, <45>, <46>, <47>,
135+
<48>, <49>, <50>, <51>, <52>, <53>, <54>,
136+
<55>, <56>, <57>, <58>, <59>, <60>, <61>,
137+
<62>, <63>, <64>, <65>;
137138
gpio-controller;
138139
ngpios = <32>;
139140
};
140141

141142
dmac0: dma-controller@50000000 {
142143
compatible = "snps,axi-dma-1.01a";
143144
reg = <0x50000000 0x1000>;
144-
interrupts = <27 28 29 30 31 32>;
145+
interrupts = <27>, <28>, <29>, <30>, <31>, <32>;
145146
#dma-cells = <1>;
146147
clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>;
147148
clock-names = "core-clk", "cfgr-clk";
@@ -316,7 +317,7 @@
316317
timer0: timer@502d0000 {
317318
compatible = "snps,dw-apb-timer";
318319
reg = <0x502D0000 0x100>;
319-
interrupts = <14 15>;
320+
interrupts = <14>, <15>;
320321
clocks = <&sysclk K210_CLK_TIMER0>,
321322
<&sysclk K210_CLK_APB0>;
322323
clock-names = "timer", "pclk";
@@ -326,7 +327,7 @@
326327
timer1: timer@502e0000 {
327328
compatible = "snps,dw-apb-timer";
328329
reg = <0x502E0000 0x100>;
329-
interrupts = <16 17>;
330+
interrupts = <16>, <17>;
330331
clocks = <&sysclk K210_CLK_TIMER1>,
331332
<&sysclk K210_CLK_APB0>;
332333
clock-names = "timer", "pclk";
@@ -336,7 +337,7 @@
336337
timer2: timer@502f0000 {
337338
compatible = "snps,dw-apb-timer";
338339
reg = <0x502F0000 0x100>;
339-
interrupts = <18 19>;
340+
interrupts = <18>, <19>;
340341
clocks = <&sysclk K210_CLK_TIMER2>,
341342
<&sysclk K210_CLK_APB0>;
342343
clock-names = "timer", "pclk";

arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -199,7 +199,7 @@
199199
};
200200

201201
&spi3 {
202-
spi-flash@0 {
202+
flash@0 {
203203
compatible = "jedec,spi-nor";
204204
reg = <0>;
205205
spi-max-frequency = <50000000>;

arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -201,7 +201,7 @@
201201
};
202202

203203
&spi3 {
204-
spi-flash@0 {
204+
flash@0 {
205205
compatible = "jedec,spi-nor";
206206
reg = <0>;
207207
spi-max-frequency = <50000000>;

arch/riscv/boot/dts/canaan/sipeed_maix_go.dts

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -209,7 +209,7 @@
209209
};
210210

211211
&spi3 {
212-
spi-flash@0 {
212+
flash@0 {
213213
compatible = "jedec,spi-nor";
214214
reg = <0>;
215215
spi-max-frequency = <50000000>;

arch/riscv/boot/dts/canaan/sipeed_maixduino.dts

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -174,7 +174,7 @@
174174
};
175175

176176
&spi3 {
177-
spi-flash@0 {
177+
flash@0 {
178178
compatible = "jedec,spi-nor";
179179
reg = <0>;
180180
spi-max-frequency = <50000000>;

arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,10 @@
3535
};
3636
};
3737

38+
&refclk {
39+
clock-frequency = <600000000>;
40+
};
41+
3842
&serial0 {
3943
status = "okay";
4044
};

arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi

Lines changed: 24 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -9,9 +9,6 @@
99
model = "Microchip PolarFire SoC";
1010
compatible = "microchip,mpfs";
1111

12-
chosen {
13-
};
14-
1512
cpus {
1613
#address-cells = <1>;
1714
#size-cells = <0>;
@@ -142,6 +139,11 @@
142139
};
143140
};
144141

142+
refclk: msspllclk {
143+
compatible = "fixed-clock";
144+
#clock-cells = <0>;
145+
};
146+
145147
soc {
146148
#address-cells = <2>;
147149
#size-cells = <2>;
@@ -156,62 +158,48 @@
156158
cache-size = <2097152>;
157159
cache-unified;
158160
interrupt-parent = <&plic>;
159-
interrupts = <1 2 3>;
161+
interrupts = <1>, <2>, <3>;
160162
reg = <0x0 0x2010000 0x0 0x1000>;
161163
};
162164

163165
clint@2000000 {
164166
compatible = "sifive,fu540-c000-clint", "sifive,clint0";
165167
reg = <0x0 0x2000000 0x0 0xC000>;
166-
interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
167-
&cpu1_intc 3 &cpu1_intc 7
168-
&cpu2_intc 3 &cpu2_intc 7
169-
&cpu3_intc 3 &cpu3_intc 7
170-
&cpu4_intc 3 &cpu4_intc 7>;
168+
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
169+
<&cpu1_intc 3>, <&cpu1_intc 7>,
170+
<&cpu2_intc 3>, <&cpu2_intc 7>,
171+
<&cpu3_intc 3>, <&cpu3_intc 7>,
172+
<&cpu4_intc 3>, <&cpu4_intc 7>;
171173
};
172174

173175
plic: interrupt-controller@c000000 {
174-
#interrupt-cells = <1>;
175176
compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
176177
reg = <0x0 0xc000000 0x0 0x4000000>;
177-
riscv,ndev = <186>;
178+
#address-cells = <0>;
179+
#interrupt-cells = <1>;
178180
interrupt-controller;
179-
interrupts-extended = <&cpu0_intc 11
180-
&cpu1_intc 11 &cpu1_intc 9
181-
&cpu2_intc 11 &cpu2_intc 9
182-
&cpu3_intc 11 &cpu3_intc 9
183-
&cpu4_intc 11 &cpu4_intc 9>;
181+
interrupts-extended = <&cpu0_intc 11>,
182+
<&cpu1_intc 11>, <&cpu1_intc 9>,
183+
<&cpu2_intc 11>, <&cpu2_intc 9>,
184+
<&cpu3_intc 11>, <&cpu3_intc 9>,
185+
<&cpu4_intc 11>, <&cpu4_intc 9>;
186+
riscv,ndev = <186>;
184187
};
185188

186189
dma@3000000 {
187190
compatible = "sifive,fu540-c000-pdma";
188191
reg = <0x0 0x3000000 0x0 0x8000>;
189192
interrupt-parent = <&plic>;
190-
interrupts = <23 24 25 26 27 28 29 30>;
193+
interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
194+
<30>;
191195
#dma-cells = <1>;
192196
};
193197

194-
refclk: refclk {
195-
compatible = "fixed-clock";
196-
#clock-cells = <0>;
197-
clock-frequency = <600000000>;
198-
clock-output-names = "msspllclk";
199-
};
200-
201198
clkcfg: clkcfg@20002000 {
202199
compatible = "microchip,mpfs-clkcfg";
203200
reg = <0x0 0x20002000 0x0 0x1000>;
204-
reg-names = "mss_sysreg";
205201
clocks = <&refclk>;
206202
#clock-cells = <1>;
207-
clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */
208-
"mac0", "mac1", "mmc", "timer", /* 4-7 */
209-
"mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */
210-
"mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */
211-
"i2c1", "can0", "can1", "usb", /* 16-19 */
212-
"rsvd", "rtc", "qspi", "gpio0", /* 20-23 */
213-
"gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */
214-
"fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */
215203
};
216204

217205
serial0: serial@20000000 {
@@ -267,7 +255,7 @@
267255
compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
268256
reg = <0x0 0x20008000 0x0 0x1000>;
269257
interrupt-parent = <&plic>;
270-
interrupts = <88 89>;
258+
interrupts = <88>, <89>;
271259
clocks = <&clkcfg 6>;
272260
max-frequency = <200000000>;
273261
status = "disabled";
@@ -277,7 +265,7 @@
277265
compatible = "cdns,macb";
278266
reg = <0x0 0x20110000 0x0 0x2000>;
279267
interrupt-parent = <&plic>;
280-
interrupts = <64 65 66 67>;
268+
interrupts = <64>, <65>, <66>, <67>;
281269
local-mac-address = [00 00 00 00 00 00];
282270
clocks = <&clkcfg 4>, <&clkcfg 2>;
283271
clock-names = "pclk", "hclk";
@@ -290,7 +278,7 @@
290278
compatible = "cdns,macb";
291279
reg = <0x0 0x20112000 0x0 0x2000>;
292280
interrupt-parent = <&plic>;
293-
interrupts = <70 71 72 73>;
281+
interrupts = <70>, <71>, <72>, <73>;
294282
local-mac-address = [00 00 00 00 00 00];
295283
clocks = <&clkcfg 5>, <&clkcfg 2>;
296284
status = "disabled";

arch/riscv/boot/dts/sifive/fu540-c000.dtsi

Lines changed: 21 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -137,20 +137,21 @@
137137
soc {
138138
#address-cells = <2>;
139139
#size-cells = <2>;
140-
compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
140+
compatible = "simple-bus";
141141
ranges;
142142
plic0: interrupt-controller@c000000 {
143-
#interrupt-cells = <1>;
144143
compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
145144
reg = <0x0 0xc000000 0x0 0x4000000>;
146-
riscv,ndev = <53>;
145+
#address-cells = <0>;
146+
#interrupt-cells = <1>;
147147
interrupt-controller;
148-
interrupts-extended = <
149-
&cpu0_intc 0xffffffff
150-
&cpu1_intc 0xffffffff &cpu1_intc 9
151-
&cpu2_intc 0xffffffff &cpu2_intc 9
152-
&cpu3_intc 0xffffffff &cpu3_intc 9
153-
&cpu4_intc 0xffffffff &cpu4_intc 9>;
148+
interrupts-extended =
149+
<&cpu0_intc 0xffffffff>,
150+
<&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
151+
<&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
152+
<&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
153+
<&cpu4_intc 0xffffffff>, <&cpu4_intc 9>;
154+
riscv,ndev = <53>;
154155
};
155156
prci: clock-controller@10000000 {
156157
compatible = "sifive,fu540-c000-prci";
@@ -170,7 +171,8 @@
170171
compatible = "sifive,fu540-c000-pdma";
171172
reg = <0x0 0x3000000 0x0 0x8000>;
172173
interrupt-parent = <&plic0>;
173-
interrupts = <23 24 25 26 27 28 29 30>;
174+
interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
175+
<30>;
174176
#dma-cells = <1>;
175177
};
176178
uart1: serial@10011000 {
@@ -195,8 +197,8 @@
195197
};
196198
qspi0: spi@10040000 {
197199
compatible = "sifive,fu540-c000-spi", "sifive,spi0";
198-
reg = <0x0 0x10040000 0x0 0x1000
199-
0x0 0x20000000 0x0 0x10000000>;
200+
reg = <0x0 0x10040000 0x0 0x1000>,
201+
<0x0 0x20000000 0x0 0x10000000>;
200202
interrupt-parent = <&plic0>;
201203
interrupts = <51>;
202204
clocks = <&prci PRCI_CLK_TLCLK>;
@@ -206,8 +208,8 @@
206208
};
207209
qspi1: spi@10041000 {
208210
compatible = "sifive,fu540-c000-spi", "sifive,spi0";
209-
reg = <0x0 0x10041000 0x0 0x1000
210-
0x0 0x30000000 0x0 0x10000000>;
211+
reg = <0x0 0x10041000 0x0 0x1000>,
212+
<0x0 0x30000000 0x0 0x10000000>;
211213
interrupt-parent = <&plic0>;
212214
interrupts = <52>;
213215
clocks = <&prci PRCI_CLK_TLCLK>;
@@ -229,8 +231,8 @@
229231
compatible = "sifive,fu540-c000-gem";
230232
interrupt-parent = <&plic0>;
231233
interrupts = <53>;
232-
reg = <0x0 0x10090000 0x0 0x2000
233-
0x0 0x100a0000 0x0 0x1000>;
234+
reg = <0x0 0x10090000 0x0 0x2000>,
235+
<0x0 0x100a0000 0x0 0x1000>;
234236
local-mac-address = [00 00 00 00 00 00];
235237
clock-names = "pclk", "hclk";
236238
clocks = <&prci PRCI_CLK_GEMGXLPLL>,
@@ -243,7 +245,7 @@
243245
compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
244246
reg = <0x0 0x10020000 0x0 0x1000>;
245247
interrupt-parent = <&plic0>;
246-
interrupts = <42 43 44 45>;
248+
interrupts = <42>, <43>, <44>, <45>;
247249
clocks = <&prci PRCI_CLK_TLCLK>;
248250
#pwm-cells = <3>;
249251
status = "disabled";
@@ -252,7 +254,7 @@
252254
compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
253255
reg = <0x0 0x10021000 0x0 0x1000>;
254256
interrupt-parent = <&plic0>;
255-
interrupts = <46 47 48 49>;
257+
interrupts = <46>, <47>, <48>, <49>;
256258
clocks = <&prci PRCI_CLK_TLCLK>;
257259
#pwm-cells = <3>;
258260
status = "disabled";
@@ -265,7 +267,7 @@
265267
cache-size = <2097152>;
266268
cache-unified;
267269
interrupt-parent = <&plic0>;
268-
interrupts = <1 2 3>;
270+
interrupts = <1>, <2>, <3>;
269271
reg = <0x0 0x2010000 0x0 0x1000>;
270272
};
271273
gpio: gpio@10060000 {

0 commit comments

Comments
 (0)