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kilograhamkilograham
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Hardware struct regeneration (#613)
* Use reg[0] description for hardware structs register arrays * Update struct headers to match SVD and latest svd2struct
1 parent a0450d0 commit 68571ad

31 files changed

+251
-32
lines changed

‎src/rp2040/hardware_structs/include/hardware/structs/adc.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
#include "hardware/address_mapped.h"
1313
#include "hardware/regs/adc.h"
1414

15-
// Reference to datasheet: https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf#tab-registerlist_adc
15+
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_adc
1616
//
1717
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
1818
// _REG_(x) will link to the corresponding register in hardware/regs/adc.h.

‎src/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
#include "hardware/address_mapped.h"
1313
#include "hardware/regs/busctrl.h"
1414

15-
// Reference to datasheet: https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf#tab-registerlist_busctrl
15+
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_busctrl
1616
//
1717
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
1818
// _REG_(x) will link to the corresponding register in hardware/regs/busctrl.h.

‎src/rp2040/hardware_structs/include/hardware/structs/clocks.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
#include "hardware/address_mapped.h"
1313
#include "hardware/regs/clocks.h"
1414

15-
// Reference to datasheet: https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf#tab-registerlist_clocks
15+
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_clocks
1616
//
1717
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
1818
// _REG_(x) will link to the corresponding register in hardware/regs/clocks.h.

‎src/rp2040/hardware_structs/include/hardware/structs/dma.h

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
#include "hardware/address_mapped.h"
1313
#include "hardware/regs/dma.h"
1414

15-
// Reference to datasheet: https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf#tab-registerlist_dma
15+
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_dma
1616
//
1717
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
1818
// _REG_(x) will link to the corresponding register in hardware/regs/dma.h.
@@ -145,6 +145,11 @@ typedef struct {
145145
io_rw_32 ints1;
146146

147147
_REG_(DMA_TIMER0_OFFSET) // DMA_TIMER0
148+
// (Description copied from array index 0 register DMA_TIMER0 applies similarly to other array indexes)
149+
//
150+
// Pacing (X/Y) Fractional Timer
151+
// 0xffff0000 [31:16] : X (0): Pacing Timer Dividend
152+
// 0x0000ffff [15:0] : Y (0): Pacing Timer Divisor
148153
io_rw_32 timer[NUM_DMA_TIMERS]; // 4
149154

150155
_REG_(DMA_MULTI_CHAN_TRIGGER_OFFSET) // DMA_MULTI_CHAN_TRIGGER
@@ -183,7 +188,7 @@ typedef struct {
183188

184189
typedef struct {
185190
struct dma_debug_hw_channel {
186-
io_ro_32 ctrdeq;
191+
io_rw_32 ctrdeq;
187192
io_ro_32 tcr;
188193
uint32_t pad[14];
189194
} ch[NUM_DMA_CHANNELS];

‎src/rp2040/hardware_structs/include/hardware/structs/i2c.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
#include "hardware/address_mapped.h"
1313
#include "hardware/regs/i2c.h"
1414

15-
// Reference to datasheet: https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf#tab-registerlist_i2c
15+
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_i2c
1616
//
1717
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
1818
// _REG_(x) will link to the corresponding register in hardware/regs/i2c.h.

‎src/rp2040/hardware_structs/include/hardware/structs/interp.h

Lines changed: 32 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
#include "hardware/address_mapped.h"
1313
#include "hardware/regs/sio.h"
1414

15-
// Reference to datasheet: https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio
15+
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio
1616
//
1717
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
1818
// _REG_(x) will link to the corresponding register in hardware/regs/sio.h.
@@ -22,21 +22,52 @@
2222

2323
typedef struct {
2424
_REG_(SIO_INTERP0_ACCUM0_OFFSET) // SIO_INTERP0_ACCUM0
25+
// (Description copied from array index 0 register SIO_INTERP0_ACCUM0 applies similarly to other array indexes)
26+
//
27+
// Read/write access to accumulator 0
2528
io_rw_32 accum[2];
2629

2730
_REG_(SIO_INTERP0_BASE0_OFFSET) // SIO_INTERP0_BASE0
31+
// (Description copied from array index 0 register SIO_INTERP0_BASE0 applies similarly to other array indexes)
32+
//
33+
// Read/write access to BASE0 register
2834
io_rw_32 base[3];
2935

3036
_REG_(SIO_INTERP0_POP_LANE0_OFFSET) // SIO_INTERP0_POP_LANE0
37+
// (Description copied from array index 0 register SIO_INTERP0_POP_LANE0 applies similarly to other array indexes)
38+
//
39+
// Read LANE0 result, and simultaneously write lane results to both accumulators (POP)
3140
io_ro_32 pop[3];
3241

3342
_REG_(SIO_INTERP0_PEEK_LANE0_OFFSET) // SIO_INTERP0_PEEK_LANE0
43+
// (Description copied from array index 0 register SIO_INTERP0_PEEK_LANE0 applies similarly to other array indexes)
44+
//
45+
// Read LANE0 result, without altering any internal state (PEEK)
3446
io_ro_32 peek[3];
3547

3648
_REG_(SIO_INTERP0_CTRL_LANE0_OFFSET) // SIO_INTERP0_CTRL_LANE0
49+
// (Description copied from array index 0 register SIO_INTERP0_CTRL_LANE0 applies similarly to other array indexes)
50+
//
51+
// Control register for lane 0
52+
// 0x02000000 [25] : OVERF (0): Set if either OVERF0 or OVERF1 is set
53+
// 0x01000000 [24] : OVERF1 (0): Indicates if any masked-off MSBs in ACCUM1 are set
54+
// 0x00800000 [23] : OVERF0 (0): Indicates if any masked-off MSBs in ACCUM0 are set
55+
// 0x00200000 [21] : BLEND (0): Only present on INTERP0 on each core
56+
// 0x00180000 [20:19] : FORCE_MSB (0): ORed into bits 29:28 of the lane result presented to the processor on the bus
57+
// 0x00040000 [18] : ADD_RAW (0): If 1, mask + shift is bypassed for LANE0 result
58+
// 0x00020000 [17] : CROSS_RESULT (0): If 1, feed the opposite lane's result into this lane's accumulator on POP
59+
// 0x00010000 [16] : CROSS_INPUT (0): If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware
60+
// 0x00008000 [15] : SIGNED (0): If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits
61+
// 0x00007c00 [14:10] : MASK_MSB (0): The most-significant bit allowed to pass by the mask (inclusive)
62+
// 0x000003e0 [9:5] : MASK_LSB (0): The least-significant bit allowed to pass by the mask (inclusive)
63+
// 0x0000001f [4:0] : SHIFT (0): Logical right-shift applied to accumulator before masking
3764
io_rw_32 ctrl[2];
3865

3966
_REG_(SIO_INTERP0_ACCUM0_ADD_OFFSET) // SIO_INTERP0_ACCUM0_ADD
67+
// (Description copied from array index 0 register SIO_INTERP0_ACCUM0_ADD applies similarly to other array indexes)
68+
//
69+
// Values written here are atomically added to ACCUM0
70+
// 0x00ffffff [23:0] : INTERP0_ACCUM0_ADD (0)
4071
io_rw_32 add_raw[2];
4172

4273
_REG_(SIO_INTERP0_BASE_1AND0_OFFSET) // SIO_INTERP0_BASE_1AND0

‎src/rp2040/hardware_structs/include/hardware/structs/iobank0.h

Lines changed: 141 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
#include "hardware/address_mapped.h"
1313
#include "hardware/regs/io_bank0.h"
1414

15-
// Reference to datasheet: https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_bank0
15+
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_bank0
1616
//
1717
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
1818
// _REG_(x) will link to the corresponding register in hardware/regs/io_bank0.h.
@@ -45,12 +45,117 @@ typedef struct {
4545

4646
typedef struct {
4747
_REG_(IO_BANK0_PROC0_INTE0_OFFSET) // IO_BANK0_PROC0_INTE0
48+
// (Description copied from array index 0 register IO_BANK0_PROC0_INTE0 applies similarly to other array indexes)
49+
//
50+
// Interrupt Enable for proc0
51+
// 0x80000000 [31] : GPIO7_EDGE_HIGH (0)
52+
// 0x40000000 [30] : GPIO7_EDGE_LOW (0)
53+
// 0x20000000 [29] : GPIO7_LEVEL_HIGH (0)
54+
// 0x10000000 [28] : GPIO7_LEVEL_LOW (0)
55+
// 0x08000000 [27] : GPIO6_EDGE_HIGH (0)
56+
// 0x04000000 [26] : GPIO6_EDGE_LOW (0)
57+
// 0x02000000 [25] : GPIO6_LEVEL_HIGH (0)
58+
// 0x01000000 [24] : GPIO6_LEVEL_LOW (0)
59+
// 0x00800000 [23] : GPIO5_EDGE_HIGH (0)
60+
// 0x00400000 [22] : GPIO5_EDGE_LOW (0)
61+
// 0x00200000 [21] : GPIO5_LEVEL_HIGH (0)
62+
// 0x00100000 [20] : GPIO5_LEVEL_LOW (0)
63+
// 0x00080000 [19] : GPIO4_EDGE_HIGH (0)
64+
// 0x00040000 [18] : GPIO4_EDGE_LOW (0)
65+
// 0x00020000 [17] : GPIO4_LEVEL_HIGH (0)
66+
// 0x00010000 [16] : GPIO4_LEVEL_LOW (0)
67+
// 0x00008000 [15] : GPIO3_EDGE_HIGH (0)
68+
// 0x00004000 [14] : GPIO3_EDGE_LOW (0)
69+
// 0x00002000 [13] : GPIO3_LEVEL_HIGH (0)
70+
// 0x00001000 [12] : GPIO3_LEVEL_LOW (0)
71+
// 0x00000800 [11] : GPIO2_EDGE_HIGH (0)
72+
// 0x00000400 [10] : GPIO2_EDGE_LOW (0)
73+
// 0x00000200 [9] : GPIO2_LEVEL_HIGH (0)
74+
// 0x00000100 [8] : GPIO2_LEVEL_LOW (0)
75+
// 0x00000080 [7] : GPIO1_EDGE_HIGH (0)
76+
// 0x00000040 [6] : GPIO1_EDGE_LOW (0)
77+
// 0x00000020 [5] : GPIO1_LEVEL_HIGH (0)
78+
// 0x00000010 [4] : GPIO1_LEVEL_LOW (0)
79+
// 0x00000008 [3] : GPIO0_EDGE_HIGH (0)
80+
// 0x00000004 [2] : GPIO0_EDGE_LOW (0)
81+
// 0x00000002 [1] : GPIO0_LEVEL_HIGH (0)
82+
// 0x00000001 [0] : GPIO0_LEVEL_LOW (0)
4883
io_rw_32 inte[4];
4984

5085
_REG_(IO_BANK0_PROC0_INTF0_OFFSET) // IO_BANK0_PROC0_INTF0
86+
// (Description copied from array index 0 register IO_BANK0_PROC0_INTF0 applies similarly to other array indexes)
87+
//
88+
// Interrupt Force for proc0
89+
// 0x80000000 [31] : GPIO7_EDGE_HIGH (0)
90+
// 0x40000000 [30] : GPIO7_EDGE_LOW (0)
91+
// 0x20000000 [29] : GPIO7_LEVEL_HIGH (0)
92+
// 0x10000000 [28] : GPIO7_LEVEL_LOW (0)
93+
// 0x08000000 [27] : GPIO6_EDGE_HIGH (0)
94+
// 0x04000000 [26] : GPIO6_EDGE_LOW (0)
95+
// 0x02000000 [25] : GPIO6_LEVEL_HIGH (0)
96+
// 0x01000000 [24] : GPIO6_LEVEL_LOW (0)
97+
// 0x00800000 [23] : GPIO5_EDGE_HIGH (0)
98+
// 0x00400000 [22] : GPIO5_EDGE_LOW (0)
99+
// 0x00200000 [21] : GPIO5_LEVEL_HIGH (0)
100+
// 0x00100000 [20] : GPIO5_LEVEL_LOW (0)
101+
// 0x00080000 [19] : GPIO4_EDGE_HIGH (0)
102+
// 0x00040000 [18] : GPIO4_EDGE_LOW (0)
103+
// 0x00020000 [17] : GPIO4_LEVEL_HIGH (0)
104+
// 0x00010000 [16] : GPIO4_LEVEL_LOW (0)
105+
// 0x00008000 [15] : GPIO3_EDGE_HIGH (0)
106+
// 0x00004000 [14] : GPIO3_EDGE_LOW (0)
107+
// 0x00002000 [13] : GPIO3_LEVEL_HIGH (0)
108+
// 0x00001000 [12] : GPIO3_LEVEL_LOW (0)
109+
// 0x00000800 [11] : GPIO2_EDGE_HIGH (0)
110+
// 0x00000400 [10] : GPIO2_EDGE_LOW (0)
111+
// 0x00000200 [9] : GPIO2_LEVEL_HIGH (0)
112+
// 0x00000100 [8] : GPIO2_LEVEL_LOW (0)
113+
// 0x00000080 [7] : GPIO1_EDGE_HIGH (0)
114+
// 0x00000040 [6] : GPIO1_EDGE_LOW (0)
115+
// 0x00000020 [5] : GPIO1_LEVEL_HIGH (0)
116+
// 0x00000010 [4] : GPIO1_LEVEL_LOW (0)
117+
// 0x00000008 [3] : GPIO0_EDGE_HIGH (0)
118+
// 0x00000004 [2] : GPIO0_EDGE_LOW (0)
119+
// 0x00000002 [1] : GPIO0_LEVEL_HIGH (0)
120+
// 0x00000001 [0] : GPIO0_LEVEL_LOW (0)
51121
io_rw_32 intf[4];
52122

53123
_REG_(IO_BANK0_PROC0_INTS0_OFFSET) // IO_BANK0_PROC0_INTS0
124+
// (Description copied from array index 0 register IO_BANK0_PROC0_INTS0 applies similarly to other array indexes)
125+
//
126+
// Interrupt status after masking & forcing for proc0
127+
// 0x80000000 [31] : GPIO7_EDGE_HIGH (0)
128+
// 0x40000000 [30] : GPIO7_EDGE_LOW (0)
129+
// 0x20000000 [29] : GPIO7_LEVEL_HIGH (0)
130+
// 0x10000000 [28] : GPIO7_LEVEL_LOW (0)
131+
// 0x08000000 [27] : GPIO6_EDGE_HIGH (0)
132+
// 0x04000000 [26] : GPIO6_EDGE_LOW (0)
133+
// 0x02000000 [25] : GPIO6_LEVEL_HIGH (0)
134+
// 0x01000000 [24] : GPIO6_LEVEL_LOW (0)
135+
// 0x00800000 [23] : GPIO5_EDGE_HIGH (0)
136+
// 0x00400000 [22] : GPIO5_EDGE_LOW (0)
137+
// 0x00200000 [21] : GPIO5_LEVEL_HIGH (0)
138+
// 0x00100000 [20] : GPIO5_LEVEL_LOW (0)
139+
// 0x00080000 [19] : GPIO4_EDGE_HIGH (0)
140+
// 0x00040000 [18] : GPIO4_EDGE_LOW (0)
141+
// 0x00020000 [17] : GPIO4_LEVEL_HIGH (0)
142+
// 0x00010000 [16] : GPIO4_LEVEL_LOW (0)
143+
// 0x00008000 [15] : GPIO3_EDGE_HIGH (0)
144+
// 0x00004000 [14] : GPIO3_EDGE_LOW (0)
145+
// 0x00002000 [13] : GPIO3_LEVEL_HIGH (0)
146+
// 0x00001000 [12] : GPIO3_LEVEL_LOW (0)
147+
// 0x00000800 [11] : GPIO2_EDGE_HIGH (0)
148+
// 0x00000400 [10] : GPIO2_EDGE_LOW (0)
149+
// 0x00000200 [9] : GPIO2_LEVEL_HIGH (0)
150+
// 0x00000100 [8] : GPIO2_LEVEL_LOW (0)
151+
// 0x00000080 [7] : GPIO1_EDGE_HIGH (0)
152+
// 0x00000040 [6] : GPIO1_EDGE_LOW (0)
153+
// 0x00000020 [5] : GPIO1_LEVEL_HIGH (0)
154+
// 0x00000010 [4] : GPIO1_LEVEL_LOW (0)
155+
// 0x00000008 [3] : GPIO0_EDGE_HIGH (0)
156+
// 0x00000004 [2] : GPIO0_EDGE_LOW (0)
157+
// 0x00000002 [1] : GPIO0_LEVEL_HIGH (0)
158+
// 0x00000001 [0] : GPIO0_LEVEL_LOW (0)
54159
io_ro_32 ints[4];
55160
} io_irq_ctrl_hw_t;
56161

@@ -59,6 +164,41 @@ typedef struct {
59164
io_status_ctrl_hw_t io[NUM_BANK0_GPIOS]; // 30
60165

61166
_REG_(IO_BANK0_INTR0_OFFSET) // IO_BANK0_INTR0
167+
// (Description copied from array index 0 register IO_BANK0_INTR0 applies similarly to other array indexes)
168+
//
169+
// Raw Interrupts
170+
// 0x80000000 [31] : GPIO7_EDGE_HIGH (0)
171+
// 0x40000000 [30] : GPIO7_EDGE_LOW (0)
172+
// 0x20000000 [29] : GPIO7_LEVEL_HIGH (0)
173+
// 0x10000000 [28] : GPIO7_LEVEL_LOW (0)
174+
// 0x08000000 [27] : GPIO6_EDGE_HIGH (0)
175+
// 0x04000000 [26] : GPIO6_EDGE_LOW (0)
176+
// 0x02000000 [25] : GPIO6_LEVEL_HIGH (0)
177+
// 0x01000000 [24] : GPIO6_LEVEL_LOW (0)
178+
// 0x00800000 [23] : GPIO5_EDGE_HIGH (0)
179+
// 0x00400000 [22] : GPIO5_EDGE_LOW (0)
180+
// 0x00200000 [21] : GPIO5_LEVEL_HIGH (0)
181+
// 0x00100000 [20] : GPIO5_LEVEL_LOW (0)
182+
// 0x00080000 [19] : GPIO4_EDGE_HIGH (0)
183+
// 0x00040000 [18] : GPIO4_EDGE_LOW (0)
184+
// 0x00020000 [17] : GPIO4_LEVEL_HIGH (0)
185+
// 0x00010000 [16] : GPIO4_LEVEL_LOW (0)
186+
// 0x00008000 [15] : GPIO3_EDGE_HIGH (0)
187+
// 0x00004000 [14] : GPIO3_EDGE_LOW (0)
188+
// 0x00002000 [13] : GPIO3_LEVEL_HIGH (0)
189+
// 0x00001000 [12] : GPIO3_LEVEL_LOW (0)
190+
// 0x00000800 [11] : GPIO2_EDGE_HIGH (0)
191+
// 0x00000400 [10] : GPIO2_EDGE_LOW (0)
192+
// 0x00000200 [9] : GPIO2_LEVEL_HIGH (0)
193+
// 0x00000100 [8] : GPIO2_LEVEL_LOW (0)
194+
// 0x00000080 [7] : GPIO1_EDGE_HIGH (0)
195+
// 0x00000040 [6] : GPIO1_EDGE_LOW (0)
196+
// 0x00000020 [5] : GPIO1_LEVEL_HIGH (0)
197+
// 0x00000010 [4] : GPIO1_LEVEL_LOW (0)
198+
// 0x00000008 [3] : GPIO0_EDGE_HIGH (0)
199+
// 0x00000004 [2] : GPIO0_EDGE_LOW (0)
200+
// 0x00000002 [1] : GPIO0_LEVEL_HIGH (0)
201+
// 0x00000001 [0] : GPIO0_LEVEL_LOW (0)
62202
io_rw_32 intr[4];
63203

64204
io_irq_ctrl_hw_t proc0_irq_ctrl;

‎src/rp2040/hardware_structs/include/hardware/structs/ioqspi.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
#include "hardware/address_mapped.h"
1313
#include "hardware/regs/io_qspi.h"
1414

15-
// Reference to datasheet: https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_qspi
15+
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_qspi
1616
//
1717
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
1818
// _REG_(x) will link to the corresponding register in hardware/regs/io_qspi.h.

‎src/rp2040/hardware_structs/include/hardware/structs/mpu.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
#include "hardware/address_mapped.h"
1313
#include "hardware/regs/m0plus.h"
1414

15-
// Reference to datasheet: https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
15+
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
1616
//
1717
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
1818
// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.

‎src/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
#include "hardware/address_mapped.h"
1313
#include "hardware/regs/pads_qspi.h"
1414

15-
// Reference to datasheet: https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_qspi
15+
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_qspi
1616
//
1717
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
1818
// _REG_(x) will link to the corresponding register in hardware/regs/pads_qspi.h.
@@ -27,6 +27,16 @@ typedef struct {
2727
io_rw_32 voltage_select;
2828

2929
_REG_(PADS_QSPI_GPIO_QSPI_SCLK_OFFSET) // PADS_QSPI_GPIO_QSPI_SCLK
30+
// (Description copied from array index 0 register PADS_QSPI_GPIO_QSPI_SCLK applies similarly to other array indexes)
31+
//
32+
// Pad control register
33+
// 0x00000080 [7] : OD (0): Output disable
34+
// 0x00000040 [6] : IE (1): Input enable
35+
// 0x00000030 [5:4] : DRIVE (1): Drive strength
36+
// 0x00000008 [3] : PUE (0): Pull up enable
37+
// 0x00000004 [2] : PDE (1): Pull down enable
38+
// 0x00000002 [1] : SCHMITT (1): Enable schmitt trigger
39+
// 0x00000001 [0] : SLEWFAST (0): Slew rate control
3040
io_rw_32 io[NUM_QSPI_GPIOS]; // 6
3141
} pads_qspi_hw_t;
3242

‎src/rp2040/hardware_structs/include/hardware/structs/padsbank0.h

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
#include "hardware/address_mapped.h"
1313
#include "hardware/regs/pads_bank0.h"
1414

15-
// Reference to datasheet: https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_bank0
15+
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_bank0
1616
//
1717
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
1818
// _REG_(x) will link to the corresponding register in hardware/regs/pads_bank0.h.
@@ -27,6 +27,16 @@ typedef struct {
2727
io_rw_32 voltage_select;
2828

2929
_REG_(PADS_BANK0_GPIO0_OFFSET) // PADS_BANK0_GPIO0
30+
// (Description copied from array index 0 register PADS_BANK0_GPIO0 applies similarly to other array indexes)
31+
//
32+
// Pad control register
33+
// 0x00000080 [7] : OD (0): Output disable
34+
// 0x00000040 [6] : IE (1): Input enable
35+
// 0x00000030 [5:4] : DRIVE (1): Drive strength
36+
// 0x00000008 [3] : PUE (0): Pull up enable
37+
// 0x00000004 [2] : PDE (1): Pull down enable
38+
// 0x00000002 [1] : SCHMITT (1): Enable schmitt trigger
39+
// 0x00000001 [0] : SLEWFAST (0): Slew rate control
3040
io_rw_32 io[NUM_BANK0_GPIOS]; // 30
3141
} padsbank0_hw_t;
3242

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