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Merged
merged 3 commits into from
Oct 14, 2021
Merged

Hardware struct regeneration #613

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9824cb6
Use reg[0] description for hardware structs register arrays
kilograham Oct 12, 2021
59a0bb6
Update struct headers to match SVD and latest svd2struct
kilograham Oct 14, 2021
a7a3f11
update register array comment slightly
kilograham Oct 14, 2021
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2 changes: 1 addition & 1 deletion src/rp2040/hardware_structs/include/hardware/structs/adc.h
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Expand Up @@ -12,7 +12,7 @@
#include "hardware/address_mapped.h"
#include "hardware/regs/adc.h"

// Reference to datasheet: https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf#tab-registerlist_adc
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_adc
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/adc.h.
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2 changes: 1 addition & 1 deletion src/rp2040/hardware_structs/include/hardware/structs/bus_ctrl.h
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Expand Up @@ -12,7 +12,7 @@
#include "hardware/address_mapped.h"
#include "hardware/regs/busctrl.h"

// Reference to datasheet: https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf#tab-registerlist_busctrl
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_busctrl
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/busctrl.h.
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2 changes: 1 addition & 1 deletion src/rp2040/hardware_structs/include/hardware/structs/clocks.h
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Expand Up @@ -12,7 +12,7 @@
#include "hardware/address_mapped.h"
#include "hardware/regs/clocks.h"

// Reference to datasheet: https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf#tab-registerlist_clocks
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_clocks
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/clocks.h.
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9 changes: 7 additions & 2 deletions src/rp2040/hardware_structs/include/hardware/structs/dma.h
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Expand Up @@ -12,7 +12,7 @@
#include "hardware/address_mapped.h"
#include "hardware/regs/dma.h"

// Reference to datasheet: https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf#tab-registerlist_dma
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_dma
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/dma.h.
Expand Down Expand Up @@ -145,6 +145,11 @@ typedef struct {
io_rw_32 ints1;

_REG_(DMA_TIMER0_OFFSET) // DMA_TIMER0
// (Description copied from array index 0 register DMA_TIMER0 applies similarly to other array indexes)
//
// Pacing (X/Y) Fractional Timer
// 0xffff0000 [31:16] : X (0): Pacing Timer Dividend
// 0x0000ffff [15:0] : Y (0): Pacing Timer Divisor
io_rw_32 timer[NUM_DMA_TIMERS]; // 4

_REG_(DMA_MULTI_CHAN_TRIGGER_OFFSET) // DMA_MULTI_CHAN_TRIGGER
Expand Down Expand Up @@ -183,7 +188,7 @@ typedef struct {

typedef struct {
struct dma_debug_hw_channel {
io_ro_32 ctrdeq;
io_rw_32 ctrdeq;
io_ro_32 tcr;
uint32_t pad[14];
} ch[NUM_DMA_CHANNELS];
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2 changes: 1 addition & 1 deletion src/rp2040/hardware_structs/include/hardware/structs/i2c.h
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Expand Up @@ -12,7 +12,7 @@
#include "hardware/address_mapped.h"
#include "hardware/regs/i2c.h"

// Reference to datasheet: https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf#tab-registerlist_i2c
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_i2c
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/i2c.h.
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33 changes: 32 additions & 1 deletion src/rp2040/hardware_structs/include/hardware/structs/interp.h
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Expand Up @@ -12,7 +12,7 @@
#include "hardware/address_mapped.h"
#include "hardware/regs/sio.h"

// Reference to datasheet: https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/sio.h.
Expand All @@ -22,21 +22,52 @@

typedef struct {
_REG_(SIO_INTERP0_ACCUM0_OFFSET) // SIO_INTERP0_ACCUM0
// (Description copied from array index 0 register SIO_INTERP0_ACCUM0 applies similarly to other array indexes)
//
// Read/write access to accumulator 0
io_rw_32 accum[2];

_REG_(SIO_INTERP0_BASE0_OFFSET) // SIO_INTERP0_BASE0
// (Description copied from array index 0 register SIO_INTERP0_BASE0 applies similarly to other array indexes)
//
// Read/write access to BASE0 register
io_rw_32 base[3];

_REG_(SIO_INTERP0_POP_LANE0_OFFSET) // SIO_INTERP0_POP_LANE0
// (Description copied from array index 0 register SIO_INTERP0_POP_LANE0 applies similarly to other array indexes)
//
// Read LANE0 result, and simultaneously write lane results to both accumulators (POP)
io_ro_32 pop[3];

_REG_(SIO_INTERP0_PEEK_LANE0_OFFSET) // SIO_INTERP0_PEEK_LANE0
// (Description copied from array index 0 register SIO_INTERP0_PEEK_LANE0 applies similarly to other array indexes)
//
// Read LANE0 result, without altering any internal state (PEEK)
io_ro_32 peek[3];

_REG_(SIO_INTERP0_CTRL_LANE0_OFFSET) // SIO_INTERP0_CTRL_LANE0
// (Description copied from array index 0 register SIO_INTERP0_CTRL_LANE0 applies similarly to other array indexes)
//
// Control register for lane 0
// 0x02000000 [25] : OVERF (0): Set if either OVERF0 or OVERF1 is set
// 0x01000000 [24] : OVERF1 (0): Indicates if any masked-off MSBs in ACCUM1 are set
// 0x00800000 [23] : OVERF0 (0): Indicates if any masked-off MSBs in ACCUM0 are set
// 0x00200000 [21] : BLEND (0): Only present on INTERP0 on each core
// 0x00180000 [20:19] : FORCE_MSB (0): ORed into bits 29:28 of the lane result presented to the processor on the bus
// 0x00040000 [18] : ADD_RAW (0): If 1, mask + shift is bypassed for LANE0 result
// 0x00020000 [17] : CROSS_RESULT (0): If 1, feed the opposite lane's result into this lane's accumulator on POP
// 0x00010000 [16] : CROSS_INPUT (0): If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware
// 0x00008000 [15] : SIGNED (0): If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits
// 0x00007c00 [14:10] : MASK_MSB (0): The most-significant bit allowed to pass by the mask (inclusive)
// 0x000003e0 [9:5] : MASK_LSB (0): The least-significant bit allowed to pass by the mask (inclusive)
// 0x0000001f [4:0] : SHIFT (0): Logical right-shift applied to accumulator before masking
io_rw_32 ctrl[2];

_REG_(SIO_INTERP0_ACCUM0_ADD_OFFSET) // SIO_INTERP0_ACCUM0_ADD
// (Description copied from array index 0 register SIO_INTERP0_ACCUM0_ADD applies similarly to other array indexes)
//
// Values written here are atomically added to ACCUM0
// 0x00ffffff [23:0] : INTERP0_ACCUM0_ADD (0)
io_rw_32 add_raw[2];

_REG_(SIO_INTERP0_BASE_1AND0_OFFSET) // SIO_INTERP0_BASE_1AND0
Expand Down
142 changes: 141 additions & 1 deletion src/rp2040/hardware_structs/include/hardware/structs/iobank0.h
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Expand Up @@ -12,7 +12,7 @@
#include "hardware/address_mapped.h"
#include "hardware/regs/io_bank0.h"

// Reference to datasheet: https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_bank0
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_bank0
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/io_bank0.h.
Expand Down Expand Up @@ -45,12 +45,117 @@ typedef struct {

typedef struct {
_REG_(IO_BANK0_PROC0_INTE0_OFFSET) // IO_BANK0_PROC0_INTE0
// (Description copied from array index 0 register IO_BANK0_PROC0_INTE0 applies similarly to other array indexes)
//
// Interrupt Enable for proc0
// 0x80000000 [31] : GPIO7_EDGE_HIGH (0)
// 0x40000000 [30] : GPIO7_EDGE_LOW (0)
// 0x20000000 [29] : GPIO7_LEVEL_HIGH (0)
// 0x10000000 [28] : GPIO7_LEVEL_LOW (0)
// 0x08000000 [27] : GPIO6_EDGE_HIGH (0)
// 0x04000000 [26] : GPIO6_EDGE_LOW (0)
// 0x02000000 [25] : GPIO6_LEVEL_HIGH (0)
// 0x01000000 [24] : GPIO6_LEVEL_LOW (0)
// 0x00800000 [23] : GPIO5_EDGE_HIGH (0)
// 0x00400000 [22] : GPIO5_EDGE_LOW (0)
// 0x00200000 [21] : GPIO5_LEVEL_HIGH (0)
// 0x00100000 [20] : GPIO5_LEVEL_LOW (0)
// 0x00080000 [19] : GPIO4_EDGE_HIGH (0)
// 0x00040000 [18] : GPIO4_EDGE_LOW (0)
// 0x00020000 [17] : GPIO4_LEVEL_HIGH (0)
// 0x00010000 [16] : GPIO4_LEVEL_LOW (0)
// 0x00008000 [15] : GPIO3_EDGE_HIGH (0)
// 0x00004000 [14] : GPIO3_EDGE_LOW (0)
// 0x00002000 [13] : GPIO3_LEVEL_HIGH (0)
// 0x00001000 [12] : GPIO3_LEVEL_LOW (0)
// 0x00000800 [11] : GPIO2_EDGE_HIGH (0)
// 0x00000400 [10] : GPIO2_EDGE_LOW (0)
// 0x00000200 [9] : GPIO2_LEVEL_HIGH (0)
// 0x00000100 [8] : GPIO2_LEVEL_LOW (0)
// 0x00000080 [7] : GPIO1_EDGE_HIGH (0)
// 0x00000040 [6] : GPIO1_EDGE_LOW (0)
// 0x00000020 [5] : GPIO1_LEVEL_HIGH (0)
// 0x00000010 [4] : GPIO1_LEVEL_LOW (0)
// 0x00000008 [3] : GPIO0_EDGE_HIGH (0)
// 0x00000004 [2] : GPIO0_EDGE_LOW (0)
// 0x00000002 [1] : GPIO0_LEVEL_HIGH (0)
// 0x00000001 [0] : GPIO0_LEVEL_LOW (0)
io_rw_32 inte[4];

_REG_(IO_BANK0_PROC0_INTF0_OFFSET) // IO_BANK0_PROC0_INTF0
// (Description copied from array index 0 register IO_BANK0_PROC0_INTF0 applies similarly to other array indexes)
//
// Interrupt Force for proc0
// 0x80000000 [31] : GPIO7_EDGE_HIGH (0)
// 0x40000000 [30] : GPIO7_EDGE_LOW (0)
// 0x20000000 [29] : GPIO7_LEVEL_HIGH (0)
// 0x10000000 [28] : GPIO7_LEVEL_LOW (0)
// 0x08000000 [27] : GPIO6_EDGE_HIGH (0)
// 0x04000000 [26] : GPIO6_EDGE_LOW (0)
// 0x02000000 [25] : GPIO6_LEVEL_HIGH (0)
// 0x01000000 [24] : GPIO6_LEVEL_LOW (0)
// 0x00800000 [23] : GPIO5_EDGE_HIGH (0)
// 0x00400000 [22] : GPIO5_EDGE_LOW (0)
// 0x00200000 [21] : GPIO5_LEVEL_HIGH (0)
// 0x00100000 [20] : GPIO5_LEVEL_LOW (0)
// 0x00080000 [19] : GPIO4_EDGE_HIGH (0)
// 0x00040000 [18] : GPIO4_EDGE_LOW (0)
// 0x00020000 [17] : GPIO4_LEVEL_HIGH (0)
// 0x00010000 [16] : GPIO4_LEVEL_LOW (0)
// 0x00008000 [15] : GPIO3_EDGE_HIGH (0)
// 0x00004000 [14] : GPIO3_EDGE_LOW (0)
// 0x00002000 [13] : GPIO3_LEVEL_HIGH (0)
// 0x00001000 [12] : GPIO3_LEVEL_LOW (0)
// 0x00000800 [11] : GPIO2_EDGE_HIGH (0)
// 0x00000400 [10] : GPIO2_EDGE_LOW (0)
// 0x00000200 [9] : GPIO2_LEVEL_HIGH (0)
// 0x00000100 [8] : GPIO2_LEVEL_LOW (0)
// 0x00000080 [7] : GPIO1_EDGE_HIGH (0)
// 0x00000040 [6] : GPIO1_EDGE_LOW (0)
// 0x00000020 [5] : GPIO1_LEVEL_HIGH (0)
// 0x00000010 [4] : GPIO1_LEVEL_LOW (0)
// 0x00000008 [3] : GPIO0_EDGE_HIGH (0)
// 0x00000004 [2] : GPIO0_EDGE_LOW (0)
// 0x00000002 [1] : GPIO0_LEVEL_HIGH (0)
// 0x00000001 [0] : GPIO0_LEVEL_LOW (0)
io_rw_32 intf[4];

_REG_(IO_BANK0_PROC0_INTS0_OFFSET) // IO_BANK0_PROC0_INTS0
// (Description copied from array index 0 register IO_BANK0_PROC0_INTS0 applies similarly to other array indexes)
//
// Interrupt status after masking & forcing for proc0
// 0x80000000 [31] : GPIO7_EDGE_HIGH (0)
// 0x40000000 [30] : GPIO7_EDGE_LOW (0)
// 0x20000000 [29] : GPIO7_LEVEL_HIGH (0)
// 0x10000000 [28] : GPIO7_LEVEL_LOW (0)
// 0x08000000 [27] : GPIO6_EDGE_HIGH (0)
// 0x04000000 [26] : GPIO6_EDGE_LOW (0)
// 0x02000000 [25] : GPIO6_LEVEL_HIGH (0)
// 0x01000000 [24] : GPIO6_LEVEL_LOW (0)
// 0x00800000 [23] : GPIO5_EDGE_HIGH (0)
// 0x00400000 [22] : GPIO5_EDGE_LOW (0)
// 0x00200000 [21] : GPIO5_LEVEL_HIGH (0)
// 0x00100000 [20] : GPIO5_LEVEL_LOW (0)
// 0x00080000 [19] : GPIO4_EDGE_HIGH (0)
// 0x00040000 [18] : GPIO4_EDGE_LOW (0)
// 0x00020000 [17] : GPIO4_LEVEL_HIGH (0)
// 0x00010000 [16] : GPIO4_LEVEL_LOW (0)
// 0x00008000 [15] : GPIO3_EDGE_HIGH (0)
// 0x00004000 [14] : GPIO3_EDGE_LOW (0)
// 0x00002000 [13] : GPIO3_LEVEL_HIGH (0)
// 0x00001000 [12] : GPIO3_LEVEL_LOW (0)
// 0x00000800 [11] : GPIO2_EDGE_HIGH (0)
// 0x00000400 [10] : GPIO2_EDGE_LOW (0)
// 0x00000200 [9] : GPIO2_LEVEL_HIGH (0)
// 0x00000100 [8] : GPIO2_LEVEL_LOW (0)
// 0x00000080 [7] : GPIO1_EDGE_HIGH (0)
// 0x00000040 [6] : GPIO1_EDGE_LOW (0)
// 0x00000020 [5] : GPIO1_LEVEL_HIGH (0)
// 0x00000010 [4] : GPIO1_LEVEL_LOW (0)
// 0x00000008 [3] : GPIO0_EDGE_HIGH (0)
// 0x00000004 [2] : GPIO0_EDGE_LOW (0)
// 0x00000002 [1] : GPIO0_LEVEL_HIGH (0)
// 0x00000001 [0] : GPIO0_LEVEL_LOW (0)
io_ro_32 ints[4];
} io_irq_ctrl_hw_t;

Expand All @@ -59,6 +164,41 @@ typedef struct {
io_status_ctrl_hw_t io[NUM_BANK0_GPIOS]; // 30

_REG_(IO_BANK0_INTR0_OFFSET) // IO_BANK0_INTR0
// (Description copied from array index 0 register IO_BANK0_INTR0 applies similarly to other array indexes)
//
// Raw Interrupts
// 0x80000000 [31] : GPIO7_EDGE_HIGH (0)
// 0x40000000 [30] : GPIO7_EDGE_LOW (0)
// 0x20000000 [29] : GPIO7_LEVEL_HIGH (0)
// 0x10000000 [28] : GPIO7_LEVEL_LOW (0)
// 0x08000000 [27] : GPIO6_EDGE_HIGH (0)
// 0x04000000 [26] : GPIO6_EDGE_LOW (0)
// 0x02000000 [25] : GPIO6_LEVEL_HIGH (0)
// 0x01000000 [24] : GPIO6_LEVEL_LOW (0)
// 0x00800000 [23] : GPIO5_EDGE_HIGH (0)
// 0x00400000 [22] : GPIO5_EDGE_LOW (0)
// 0x00200000 [21] : GPIO5_LEVEL_HIGH (0)
// 0x00100000 [20] : GPIO5_LEVEL_LOW (0)
// 0x00080000 [19] : GPIO4_EDGE_HIGH (0)
// 0x00040000 [18] : GPIO4_EDGE_LOW (0)
// 0x00020000 [17] : GPIO4_LEVEL_HIGH (0)
// 0x00010000 [16] : GPIO4_LEVEL_LOW (0)
// 0x00008000 [15] : GPIO3_EDGE_HIGH (0)
// 0x00004000 [14] : GPIO3_EDGE_LOW (0)
// 0x00002000 [13] : GPIO3_LEVEL_HIGH (0)
// 0x00001000 [12] : GPIO3_LEVEL_LOW (0)
// 0x00000800 [11] : GPIO2_EDGE_HIGH (0)
// 0x00000400 [10] : GPIO2_EDGE_LOW (0)
// 0x00000200 [9] : GPIO2_LEVEL_HIGH (0)
// 0x00000100 [8] : GPIO2_LEVEL_LOW (0)
// 0x00000080 [7] : GPIO1_EDGE_HIGH (0)
// 0x00000040 [6] : GPIO1_EDGE_LOW (0)
// 0x00000020 [5] : GPIO1_LEVEL_HIGH (0)
// 0x00000010 [4] : GPIO1_LEVEL_LOW (0)
// 0x00000008 [3] : GPIO0_EDGE_HIGH (0)
// 0x00000004 [2] : GPIO0_EDGE_LOW (0)
// 0x00000002 [1] : GPIO0_LEVEL_HIGH (0)
// 0x00000001 [0] : GPIO0_LEVEL_LOW (0)
io_rw_32 intr[4];

io_irq_ctrl_hw_t proc0_irq_ctrl;
Expand Down
2 changes: 1 addition & 1 deletion src/rp2040/hardware_structs/include/hardware/structs/ioqspi.h
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Expand Up @@ -12,7 +12,7 @@
#include "hardware/address_mapped.h"
#include "hardware/regs/io_qspi.h"

// Reference to datasheet: https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_qspi
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_qspi
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/io_qspi.h.
Expand Down
2 changes: 1 addition & 1 deletion src/rp2040/hardware_structs/include/hardware/structs/mpu.h
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Expand Up @@ -12,7 +12,7 @@
#include "hardware/address_mapped.h"
#include "hardware/regs/m0plus.h"

// Reference to datasheet: https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
Expand Down
12 changes: 11 additions & 1 deletion src/rp2040/hardware_structs/include/hardware/structs/pads_qspi.h
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Expand Up @@ -12,7 +12,7 @@
#include "hardware/address_mapped.h"
#include "hardware/regs/pads_qspi.h"

// Reference to datasheet: https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_qspi
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_qspi
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/pads_qspi.h.
Expand All @@ -27,6 +27,16 @@ typedef struct {
io_rw_32 voltage_select;

_REG_(PADS_QSPI_GPIO_QSPI_SCLK_OFFSET) // PADS_QSPI_GPIO_QSPI_SCLK
// (Description copied from array index 0 register PADS_QSPI_GPIO_QSPI_SCLK applies similarly to other array indexes)
//
// Pad control register
// 0x00000080 [7] : OD (0): Output disable
// 0x00000040 [6] : IE (1): Input enable
// 0x00000030 [5:4] : DRIVE (1): Drive strength
// 0x00000008 [3] : PUE (0): Pull up enable
// 0x00000004 [2] : PDE (1): Pull down enable
// 0x00000002 [1] : SCHMITT (1): Enable schmitt trigger
// 0x00000001 [0] : SLEWFAST (0): Slew rate control
io_rw_32 io[NUM_QSPI_GPIOS]; // 6
} pads_qspi_hw_t;

Expand Down
12 changes: 11 additions & 1 deletion src/rp2040/hardware_structs/include/hardware/structs/padsbank0.h
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Expand Up @@ -12,7 +12,7 @@
#include "hardware/address_mapped.h"
#include "hardware/regs/pads_bank0.h"

// Reference to datasheet: https://datasheets.raspberrypi.org/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_bank0
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_bank0
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/pads_bank0.h.
Expand All @@ -27,6 +27,16 @@ typedef struct {
io_rw_32 voltage_select;

_REG_(PADS_BANK0_GPIO0_OFFSET) // PADS_BANK0_GPIO0
// (Description copied from array index 0 register PADS_BANK0_GPIO0 applies similarly to other array indexes)
//
// Pad control register
// 0x00000080 [7] : OD (0): Output disable
// 0x00000040 [6] : IE (1): Input enable
// 0x00000030 [5:4] : DRIVE (1): Drive strength
// 0x00000008 [3] : PUE (0): Pull up enable
// 0x00000004 [2] : PDE (1): Pull down enable
// 0x00000002 [1] : SCHMITT (1): Enable schmitt trigger
// 0x00000001 [0] : SLEWFAST (0): Slew rate control
io_rw_32 io[NUM_BANK0_GPIOS]; // 30
} padsbank0_hw_t;

Expand Down
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