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Add DCB::enable_trace() and DCB::disable_trace() #111

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Merged
merged 10 commits into from
Sep 6, 2018
Merged

Add DCB::enable_trace() and DCB::disable_trace() #111

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afb4dca
Add DCB::enable_trace() and DCB::disable_trace()
kellerkindt Sep 2, 2018
c318a66
Increase version to 0.5.7
kellerkindt Sep 2, 2018
3cda015
Remvoe newline
kellerkindt Sep 2, 2018
b739654
Be more verbose about the bit being set / reset
kellerkindt Sep 2, 2018
49a6dae
Move shift-constant 24 to BIT_TRACENA
kellerkindt Sep 5, 2018
e6f511a
Move the whole shift to the constant
kellerkindt Sep 5, 2018
385b3eb
Fix typo
kellerkindt Sep 5, 2018
da13bee
Rename BIT_TRCENA to DCB_DEMCR_TRCENA, replace 0x01 with 1
kellerkindt Sep 5, 2018
b0f5ee6
No longer bump the version to 0.5.7
kellerkindt Sep 5, 2018
9b74fda
Remove newline, making the Cargo.toml 'untouched'
kellerkindt Sep 5, 2018
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21 changes: 21 additions & 0 deletions src/peripheral/dcb.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,10 @@

use volatile_register::{RW, WO};

use peripheral::DCB;

const DCB_DEMCR_TRCENA: u32 = 1 << 24;

/// Register block
#[repr(C)]
pub struct RegisterBlock {
Expand All @@ -14,3 +18,20 @@ pub struct RegisterBlock {
/// Debug Exception and Monitor Control
pub demcr: RW<u32>,
}

impl DCB {
/// Enables TRACE. This is for example required by the
/// `peripheral::DWT` cycle counter to work properly.
/// As by STM documentation, this flag is not reset on
/// soft-reset, only on power reset.
pub fn enable_trace(&mut self) {
// set bit 24 / TRCENA
unsafe { self.demcr.modify(|w| w | DCB_DEMCR_TRCENA); }
}

/// Disables TRACE. See `DCB::enable_trace()` for more details
pub fn disable_trace(&mut self) {
// unset bit 24 / TRCENA
unsafe { self.demcr.modify(|w| w & !DCB_DEMCR_TRCENA); }
}
}