Cortex M0(+) DWT fixes #127
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Detail for DWT can be found here: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf |
korken89
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korken89
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There, I think this is ready. Comment/suggestions @rust-embedded/cortex-m ? |
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This is technically a breaking change because it makes code like this: let cyccnt = &p.DWT.cyccnt;stop compiling (when target = thumbv6) so this should be merged when we are ready to release v0.6.0. |
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Indeed, but it is a bug now so a break is inevitable. |
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I tend to agree with @korken89 here. This is preventing the use of undefined behaviour (most likely even a crash) so it has precedence over "a breaking change" and thus should go in ASAP. |
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Merging in preparation of releasing 0.6.0. bors r+ |
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👎 Rejected by too few approved reviews |
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97: Rename `shcrs` to `shcsr` in `scb::RegisterBlock` r=adamgreig a=rajivr Commit `c290aa4e` introduced `shcrs` field to `scb::RegisterBlock`. In CMSIS, this field is `shcsr`. https://github.com/ARM-software/CMSIS_5/blob/5.3.0/CMSIS/Core/Include/core_cm4.h#L449 This patch changes `shcrs` to `shcsr`. Signed-off-by: Rajiv Ranganath <[email protected]> 106: Stir register and debugger check r=adamgreig a=thenewwazoo Adds support for requesting an interrupt via the STIR register and checking whether a debugger is attached. 127: Cortex M0(+) DWT fixes r=adamgreig a=korken89 The current DWT setup has a lot of registers that are not available in Cortex-M0(+), fixes are added here. Co-authored-by: Rajiv Ranganath <[email protected]> Co-authored-by: Brandon Matthews <[email protected]> Co-authored-by: Brandon Matthews <[email protected]> Co-authored-by: Emil Fresk <[email protected]>
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106: Stir register and debugger check r=adamgreig a=thenewwazoo Adds support for requesting an interrupt via the STIR register and checking whether a debugger is attached. 127: Cortex M0(+) DWT fixes r=adamgreig a=korken89 The current DWT setup has a lot of registers that are not available in Cortex-M0(+), fixes are added here. Co-authored-by: Brandon Matthews <[email protected]> Co-authored-by: Brandon Matthews <[email protected]> Co-authored-by: Emil Fresk <[email protected]>
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127: Cortex M0(+) DWT fixes r=adamgreig a=korken89 The current DWT setup has a lot of registers that are not available in Cortex-M0(+), fixes are added here. Co-authored-by: Emil Fresk <[email protected]>
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127: bump the syn dependency r=therealprof a=japaric
and switch to the recommended way to parse tokens: `parse_macro_input!`.
This improves (?) error messages when the user applies one of our attributes to
an item that's not a function.
Consider
``` rust
#[entry]
static MAIN: () = ();
```
The error message changed from:
```
error: custom attribute panicked
--> src/main.rs:10:1
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10 | #[entry]
| ^^^^^^^^
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= help: message: `#[entry]` must be applied to a function: ParseError(Some("failed to parse fn item: failed to parse"))
```
to:
```
error: expected `fn`
--> src/main.rs:11:1
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11 | static MAIN: () = ();
| ^^^^^^
error: aborting due to previous error
```
---
Before landing this I'd like to hear more details about #125 to see if this
helps
Co-authored-by: Jorge Aparicio <[email protected]>
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The current DWT setup has a lot of registers that are not available in Cortex-M0(+), fixes are added here.