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[RISCV] Fix crash in lowerVECTOR_INTERLEAVE when VecVT is an LMUL=8 type.
If VecVT is an LMUL=8 VT, we can't concatenate the vectors as that would create an illegal type. Instead we need to split the vectors and emit two VECTOR_INTERLEAVE operations that can each be lowered. Reviewed By: fakepaper56 Differential Revision: https://reviews.llvm.org/D152411
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‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

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Original file line numberDiff line numberDiff line change
@@ -7712,6 +7712,24 @@ SDValue RISCVTargetLowering::lowerVECTOR_INTERLEAVE(SDValue Op,
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MVT XLenVT = Subtarget.getXLenVT();
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SDValue VL = DAG.getRegister(RISCV::X0, XLenVT);
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// If the VT is LMUL=8, we need to split and reassemble.
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if (VecVT.getSizeInBits().getKnownMinValue() == (8 * RISCV::RVVBitsPerBlock)) {
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auto [Op0Lo, Op0Hi] = DAG.SplitVectorOperand(Op.getNode(), 0);
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auto [Op1Lo, Op1Hi] = DAG.SplitVectorOperand(Op.getNode(), 1);
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EVT SplitVT = Op0Lo.getValueType();
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SDValue ResLo = DAG.getNode(ISD::VECTOR_INTERLEAVE, DL,
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DAG.getVTList(SplitVT, SplitVT), Op0Lo, Op1Lo);
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SDValue ResHi = DAG.getNode(ISD::VECTOR_INTERLEAVE, DL,
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DAG.getVTList(SplitVT, SplitVT), Op0Hi, Op1Hi);
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SDValue Lo = DAG.getNode(ISD::CONCAT_VECTORS, DL, VecVT,
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ResLo.getValue(0), ResLo.getValue(1));
7728+
SDValue Hi = DAG.getNode(ISD::CONCAT_VECTORS, DL, VecVT,
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ResHi.getValue(0), ResHi.getValue(1));
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return DAG.getMergeValues({Lo, Hi}, DL);
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}
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SDValue Interleaved;
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// If the element type is smaller than ELEN, then we can interleave with

‎llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll

Lines changed: 218 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -93,6 +93,137 @@ declare <vscale x 16 x i16> @llvm.experimental.vector.interleave2.nxv16i16(<vsca
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declare <vscale x 8 x i32> @llvm.experimental.vector.interleave2.nxv8i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 4 x i64> @llvm.experimental.vector.interleave2.nxv4i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
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define <vscale x 128 x i1> @vector_interleave_nxv128i1_nxv64i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b) {
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; CHECK-LABEL: vector_interleave_nxv128i1_nxv64i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv1r.v v9, v0
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; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
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; CHECK-NEXT: vmv.v.i v24, 0
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; CHECK-NEXT: vmv1r.v v0, v8
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; CHECK-NEXT: vmerge.vim v16, v24, 1, v0
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; CHECK-NEXT: vmv1r.v v0, v9
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; CHECK-NEXT: vmerge.vim v8, v24, 1, v0
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; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
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; CHECK-NEXT: vwaddu.vv v24, v8, v16
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; CHECK-NEXT: li a0, -1
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; CHECK-NEXT: vwmaccu.vx v24, a0, v16
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; CHECK-NEXT: vsetvli a1, zero, e8, m8, ta, ma
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; CHECK-NEXT: vmsne.vi v0, v24, 0
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; CHECK-NEXT: vsetvli a1, zero, e8, m4, ta, ma
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; CHECK-NEXT: vwaddu.vv v24, v12, v20
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; CHECK-NEXT: vwmaccu.vx v24, a0, v20
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; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
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; CHECK-NEXT: vmsne.vi v8, v24, 0
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; CHECK-NEXT: ret
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%res = call <vscale x 128 x i1> @llvm.experimental.vector.interleave2.nxv128i1(<vscale x 64 x i1> %a, <vscale x 64 x i1> %b)
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ret <vscale x 128 x i1> %res
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}
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define <vscale x 128 x i8> @vector_interleave_nxv128i8_nxv64i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b) {
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; CHECK-LABEL: vector_interleave_nxv128i8_nxv64i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv8r.v v24, v8
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; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
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; CHECK-NEXT: vwaddu.vv v8, v24, v16
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; CHECK-NEXT: li a0, -1
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; CHECK-NEXT: vwmaccu.vx v8, a0, v16
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; CHECK-NEXT: vwaddu.vv v0, v28, v20
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; CHECK-NEXT: vwmaccu.vx v0, a0, v20
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; CHECK-NEXT: vmv8r.v v16, v0
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; CHECK-NEXT: ret
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%res = call <vscale x 128 x i8> @llvm.experimental.vector.interleave2.nxv128i8(<vscale x 64 x i8> %a, <vscale x 64 x i8> %b)
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ret <vscale x 128 x i8> %res
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}
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define <vscale x 64 x i16> @vector_interleave_nxv64i16_nxv32i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b) {
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; CHECK-LABEL: vector_interleave_nxv64i16_nxv32i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv8r.v v24, v8
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; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
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; CHECK-NEXT: vwaddu.vv v8, v24, v16
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; CHECK-NEXT: li a0, -1
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; CHECK-NEXT: vwmaccu.vx v8, a0, v16
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; CHECK-NEXT: vwaddu.vv v0, v28, v20
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; CHECK-NEXT: vwmaccu.vx v0, a0, v20
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; CHECK-NEXT: vmv8r.v v16, v0
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; CHECK-NEXT: ret
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%res = call <vscale x 64 x i16> @llvm.experimental.vector.interleave2.nxv64i16(<vscale x 32 x i16> %a, <vscale x 32 x i16> %b)
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ret <vscale x 64 x i16> %res
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}
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define <vscale x 32 x i32> @vector_interleave_nxv32i32_nxv16i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b) {
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; CHECK-LABEL: vector_interleave_nxv32i32_nxv16i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv8r.v v24, v8
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; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
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; CHECK-NEXT: vwaddu.vv v8, v24, v16
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; CHECK-NEXT: li a0, -1
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; CHECK-NEXT: vwmaccu.vx v8, a0, v16
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; CHECK-NEXT: vwaddu.vv v0, v28, v20
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; CHECK-NEXT: vwmaccu.vx v0, a0, v20
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; CHECK-NEXT: vmv8r.v v16, v0
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; CHECK-NEXT: ret
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%res = call <vscale x 32 x i32> @llvm.experimental.vector.interleave2.nxv32i32(<vscale x 16 x i32> %a, <vscale x 16 x i32> %b)
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ret <vscale x 32 x i32> %res
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}
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define <vscale x 16 x i64> @vector_interleave_nxv16i64_nxv8i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b) {
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; CHECK-LABEL: vector_interleave_nxv16i64_nxv8i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: slli a0, a0, 4
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; CHECK-NEXT: sub sp, sp, a0
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; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: slli a0, a0, 3
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; CHECK-NEXT: add a0, sp, a0
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; CHECK-NEXT: addi a0, a0, 16
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; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: srli a0, a0, 1
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; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
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; CHECK-NEXT: vid.v v24
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; CHECK-NEXT: vand.vi v26, v24, 1
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; CHECK-NEXT: vmsne.vi v0, v26, 0
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; CHECK-NEXT: vsrl.vi v2, v24, 1
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; CHECK-NEXT: csrr a1, vlenb
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; CHECK-NEXT: slli a1, a1, 3
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; CHECK-NEXT: add a1, sp, a1
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; CHECK-NEXT: addi a1, a1, 16
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; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
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; CHECK-NEXT: vadd.vx v2, v2, a0, v0.t
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; CHECK-NEXT: vmv4r.v v12, v16
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; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
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; CHECK-NEXT: vrgatherei16.vv v24, v8, v2, v0.t
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; CHECK-NEXT: addi a0, sp, 16
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; CHECK-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: slli a0, a0, 3
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; CHECK-NEXT: add a0, sp, a0
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; CHECK-NEXT: addi a0, a0, 16
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; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
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; CHECK-NEXT: vmv4r.v v16, v12
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; CHECK-NEXT: vrgatherei16.vv v24, v16, v2, v0.t
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; CHECK-NEXT: addi a0, sp, 16
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; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
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; CHECK-NEXT: vmv.v.v v16, v24
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: slli a0, a0, 4
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; CHECK-NEXT: add sp, sp, a0
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; CHECK-NEXT: addi sp, sp, 16
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; CHECK-NEXT: ret
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%res = call <vscale x 16 x i64> @llvm.experimental.vector.interleave2.nxv16i64(<vscale x 8 x i64> %a, <vscale x 8 x i64> %b)
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ret <vscale x 16 x i64> %res
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}
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declare <vscale x 128 x i1> @llvm.experimental.vector.interleave2.nxv128i1(<vscale x 64 x i1>, <vscale x 64 x i1>)
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declare <vscale x 128 x i8> @llvm.experimental.vector.interleave2.nxv128i8(<vscale x 64 x i8>, <vscale x 64 x i8>)
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declare <vscale x 64 x i16> @llvm.experimental.vector.interleave2.nxv64i16(<vscale x 32 x i16>, <vscale x 32 x i16>)
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declare <vscale x 32 x i32> @llvm.experimental.vector.interleave2.nxv32i32(<vscale x 16 x i32>, <vscale x 16 x i32>)
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declare <vscale x 16 x i64> @llvm.experimental.vector.interleave2.nxv16i64(<vscale x 8 x i64>, <vscale x 8 x i64>)
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; Floats
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98229
define <vscale x 4 x half> @vector_interleave_nxv4f16_nxv2f16(<vscale x 2 x half> %a, <vscale x 2 x half> %b) {
@@ -193,3 +324,90 @@ declare <vscale x 4 x float> @llvm.experimental.vector.interleave2.nxv4f32(<vsca
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declare <vscale x 16 x half> @llvm.experimental.vector.interleave2.nxv16f16(<vscale x 8 x half>, <vscale x 8 x half>)
194325
declare <vscale x 8 x float> @llvm.experimental.vector.interleave2.nxv8f32(<vscale x 4 x float>, <vscale x 4 x float>)
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declare <vscale x 4 x double> @llvm.experimental.vector.interleave2.nxv4f64(<vscale x 2 x double>, <vscale x 2 x double>)
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define <vscale x 64 x half> @vector_interleave_nxv64f16_nxv32f16(<vscale x 32 x half> %a, <vscale x 32 x half> %b) {
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; CHECK-LABEL: vector_interleave_nxv64f16_nxv32f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv8r.v v24, v8
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; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
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; CHECK-NEXT: vwaddu.vv v8, v24, v16
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; CHECK-NEXT: li a0, -1
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; CHECK-NEXT: vwmaccu.vx v8, a0, v16
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; CHECK-NEXT: vwaddu.vv v0, v28, v20
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; CHECK-NEXT: vwmaccu.vx v0, a0, v20
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; CHECK-NEXT: vmv8r.v v16, v0
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; CHECK-NEXT: ret
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%res = call <vscale x 64 x half> @llvm.experimental.vector.interleave2.nxv64f16(<vscale x 32 x half> %a, <vscale x 32 x half> %b)
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ret <vscale x 64 x half> %res
342+
}
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define <vscale x 32 x float> @vector_interleave_nxv32f32_nxv16f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b) {
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; CHECK-LABEL: vector_interleave_nxv32f32_nxv16f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv8r.v v24, v8
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; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
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; CHECK-NEXT: vwaddu.vv v8, v24, v16
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; CHECK-NEXT: li a0, -1
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; CHECK-NEXT: vwmaccu.vx v8, a0, v16
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; CHECK-NEXT: vwaddu.vv v0, v28, v20
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; CHECK-NEXT: vwmaccu.vx v0, a0, v20
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; CHECK-NEXT: vmv8r.v v16, v0
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; CHECK-NEXT: ret
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%res = call <vscale x 32 x float> @llvm.experimental.vector.interleave2.nxv32f32(<vscale x 16 x float> %a, <vscale x 16 x float> %b)
357+
ret <vscale x 32 x float> %res
358+
}
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define <vscale x 16 x double> @vector_interleave_nxv16f64_nxv8f64(<vscale x 8 x double> %a, <vscale x 8 x double> %b) {
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; CHECK-LABEL: vector_interleave_nxv16f64_nxv8f64:
362+
; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
365+
; CHECK-NEXT: csrr a0, vlenb
366+
; CHECK-NEXT: slli a0, a0, 4
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; CHECK-NEXT: sub sp, sp, a0
368+
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
369+
; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: slli a0, a0, 3
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; CHECK-NEXT: add a0, sp, a0
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; CHECK-NEXT: addi a0, a0, 16
373+
; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
374+
; CHECK-NEXT: csrr a0, vlenb
375+
; CHECK-NEXT: srli a0, a0, 1
376+
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, mu
377+
; CHECK-NEXT: vid.v v24
378+
; CHECK-NEXT: vand.vi v26, v24, 1
379+
; CHECK-NEXT: vmsne.vi v0, v26, 0
380+
; CHECK-NEXT: vsrl.vi v2, v24, 1
381+
; CHECK-NEXT: csrr a1, vlenb
382+
; CHECK-NEXT: slli a1, a1, 3
383+
; CHECK-NEXT: add a1, sp, a1
384+
; CHECK-NEXT: addi a1, a1, 16
385+
; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
386+
; CHECK-NEXT: vadd.vx v2, v2, a0, v0.t
387+
; CHECK-NEXT: vmv4r.v v12, v16
388+
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
389+
; CHECK-NEXT: vrgatherei16.vv v24, v8, v2, v0.t
390+
; CHECK-NEXT: addi a0, sp, 16
391+
; CHECK-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
392+
; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: slli a0, a0, 3
394+
; CHECK-NEXT: add a0, sp, a0
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; CHECK-NEXT: addi a0, a0, 16
396+
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
397+
; CHECK-NEXT: vmv4r.v v16, v12
398+
; CHECK-NEXT: vrgatherei16.vv v24, v16, v2, v0.t
399+
; CHECK-NEXT: addi a0, sp, 16
400+
; CHECK-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
401+
; CHECK-NEXT: vmv.v.v v16, v24
402+
; CHECK-NEXT: csrr a0, vlenb
403+
; CHECK-NEXT: slli a0, a0, 4
404+
; CHECK-NEXT: add sp, sp, a0
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; CHECK-NEXT: addi sp, sp, 16
406+
; CHECK-NEXT: ret
407+
%res = call <vscale x 16 x double> @llvm.experimental.vector.interleave2.nxv16f64(<vscale x 8 x double> %a, <vscale x 8 x double> %b)
408+
ret <vscale x 16 x double> %res
409+
}
410+
411+
declare <vscale x 64 x half> @llvm.experimental.vector.interleave2.nxv64f16(<vscale x 32 x half>, <vscale x 32 x half>)
412+
declare <vscale x 32 x float> @llvm.experimental.vector.interleave2.nxv32f32(<vscale x 16 x float>, <vscale x 16 x float>)
413+
declare <vscale x 16 x double> @llvm.experimental.vector.interleave2.nxv16f64(<vscale x 8 x double>, <vscale x 8 x double>)

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