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[AMDGPU] Regenerate test checks after D149986
1 parent 4c6ae6e commit 55013ba

13 files changed

+860
-860
lines changed

‎llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -256,7 +256,7 @@ define void @private_ptr_foo(ptr addrspace(5) nocapture %arg) {
256256
; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
257257
; GFX940-NEXT: v_add_u32_e32 v0, 4, v0
258258
; GFX940-NEXT: v_mov_b32_e32 v1, 0x41200000
259-
; GFX940-NEXT: scratch_store_dword v0, v1, off
259+
; GFX940-NEXT: scratch_store_dword v0, v1, off sc0 sc1
260260
; GFX940-NEXT: s_waitcnt vmcnt(0)
261261
; GFX940-NEXT: s_setpc_b64 s[30:31]
262262
;

‎llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -55,7 +55,7 @@ define amdgpu_ps void @raw_buffer_atomic_add_rtn_f64(<4 x i32> inreg %rsrc, doub
5555
; GFX940: ; %bb.0: ; %main_body
5656
; GFX940-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[0:3], 0 offen sc0
5757
; GFX940-NEXT: s_waitcnt vmcnt(0)
58-
; GFX940-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
58+
; GFX940-NEXT: flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
5959
; GFX940-NEXT: s_endpgm
6060
main_body:
6161
%ret = call double @llvm.amdgcn.raw.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
@@ -91,7 +91,7 @@ define amdgpu_kernel void @raw_buffer_atomic_add_rtn_f64_off4_slc(<4 x i32> inre
9191
; GFX940-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[4:7], 4 offen sc0 nt
9292
; GFX940-NEXT: v_mov_b32_e32 v2, 0
9393
; GFX940-NEXT: s_waitcnt vmcnt(0)
94-
; GFX940-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
94+
; GFX940-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
9595
; GFX940-NEXT: s_endpgm
9696
main_body:
9797
%ret = call double @llvm.amdgcn.raw.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i32 2)
@@ -138,7 +138,7 @@ define amdgpu_ps void @struct_buffer_atomic_add_rtn_f64(<4 x i32> inreg %rsrc, d
138138
; GFX940: ; %bb.0: ; %main_body
139139
; GFX940-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[0:3], 0 idxen sc0
140140
; GFX940-NEXT: s_waitcnt vmcnt(0)
141-
; GFX940-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
141+
; GFX940-NEXT: flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
142142
; GFX940-NEXT: s_endpgm
143143
main_body:
144144
%ret = call double @llvm.amdgcn.struct.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
@@ -174,7 +174,7 @@ define amdgpu_kernel void @struct_buffer_atomic_add_rtn_f64_off4_slc(<4 x i32> i
174174
; GFX940-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[4:7], 0 idxen offset:4 sc0 nt
175175
; GFX940-NEXT: v_mov_b32_e32 v2, 0
176176
; GFX940-NEXT: s_waitcnt vmcnt(0)
177-
; GFX940-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
177+
; GFX940-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
178178
; GFX940-NEXT: s_endpgm
179179
main_body:
180180
%ret = call double @llvm.amdgcn.struct.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i32 0, i32 2)
@@ -221,7 +221,7 @@ define amdgpu_ps void @raw_buffer_atomic_min_rtn_f64(<4 x i32> inreg %rsrc, doub
221221
; GFX940: ; %bb.0: ; %main_body
222222
; GFX940-NEXT: buffer_atomic_min_f64 v[0:1], v2, s[0:3], 0 offen sc0
223223
; GFX940-NEXT: s_waitcnt vmcnt(0)
224-
; GFX940-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
224+
; GFX940-NEXT: flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
225225
; GFX940-NEXT: s_endpgm
226226
main_body:
227227
%ret = call double @llvm.amdgcn.raw.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
@@ -257,7 +257,7 @@ define amdgpu_kernel void @raw_buffer_atomic_min_rtn_f64_off4_slc(<4 x i32> inre
257257
; GFX940-NEXT: buffer_atomic_min_f64 v[0:1], v2, s[4:7], 4 offen sc0 nt
258258
; GFX940-NEXT: v_mov_b32_e32 v2, 0
259259
; GFX940-NEXT: s_waitcnt vmcnt(0)
260-
; GFX940-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
260+
; GFX940-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
261261
; GFX940-NEXT: s_endpgm
262262
main_body:
263263
%ret = call double @llvm.amdgcn.raw.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i32 2)
@@ -304,7 +304,7 @@ define amdgpu_ps void @struct_buffer_atomic_min_rtn_f64(<4 x i32> inreg %rsrc, d
304304
; GFX940: ; %bb.0: ; %main_body
305305
; GFX940-NEXT: buffer_atomic_min_f64 v[0:1], v2, s[0:3], 0 idxen sc0
306306
; GFX940-NEXT: s_waitcnt vmcnt(0)
307-
; GFX940-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
307+
; GFX940-NEXT: flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
308308
; GFX940-NEXT: s_endpgm
309309
main_body:
310310
%ret = call double @llvm.amdgcn.struct.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
@@ -340,7 +340,7 @@ define amdgpu_kernel void @struct_buffer_atomic_min_rtn_f64_off4_slc(<4 x i32> i
340340
; GFX940-NEXT: buffer_atomic_min_f64 v[0:1], v2, s[4:7], 0 idxen offset:4 sc0 nt
341341
; GFX940-NEXT: v_mov_b32_e32 v2, 0
342342
; GFX940-NEXT: s_waitcnt vmcnt(0)
343-
; GFX940-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
343+
; GFX940-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
344344
; GFX940-NEXT: s_endpgm
345345
main_body:
346346
%ret = call double @llvm.amdgcn.struct.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i32 0, i32 2)
@@ -387,7 +387,7 @@ define amdgpu_ps void @raw_buffer_atomic_max_rtn_f64(<4 x i32> inreg %rsrc, doub
387387
; GFX940: ; %bb.0: ; %main_body
388388
; GFX940-NEXT: buffer_atomic_max_f64 v[0:1], v2, s[0:3], 0 offen sc0
389389
; GFX940-NEXT: s_waitcnt vmcnt(0)
390-
; GFX940-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
390+
; GFX940-NEXT: flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
391391
; GFX940-NEXT: s_endpgm
392392
main_body:
393393
%ret = call double @llvm.amdgcn.raw.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
@@ -423,7 +423,7 @@ define amdgpu_kernel void @raw_buffer_atomic_max_rtn_f64_off4_slc(<4 x i32> inre
423423
; GFX940-NEXT: buffer_atomic_max_f64 v[0:1], v2, s[4:7], 4 offen sc0 nt
424424
; GFX940-NEXT: v_mov_b32_e32 v2, 0
425425
; GFX940-NEXT: s_waitcnt vmcnt(0)
426-
; GFX940-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
426+
; GFX940-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
427427
; GFX940-NEXT: s_endpgm
428428
main_body:
429429
%ret = call double @llvm.amdgcn.raw.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i32 2)
@@ -470,7 +470,7 @@ define amdgpu_ps void @struct_buffer_atomic_max_rtn_f64(<4 x i32> inreg %rsrc, d
470470
; GFX940: ; %bb.0: ; %main_body
471471
; GFX940-NEXT: buffer_atomic_max_f64 v[0:1], v2, s[0:3], 0 idxen sc0
472472
; GFX940-NEXT: s_waitcnt vmcnt(0)
473-
; GFX940-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
473+
; GFX940-NEXT: flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
474474
; GFX940-NEXT: s_endpgm
475475
main_body:
476476
%ret = call double @llvm.amdgcn.struct.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
@@ -506,7 +506,7 @@ define amdgpu_kernel void @struct_buffer_atomic_max_rtn_f64_off4_slc(<4 x i32> i
506506
; GFX940-NEXT: buffer_atomic_max_f64 v[0:1], v2, s[4:7], 0 idxen offset:4 sc0 nt
507507
; GFX940-NEXT: v_mov_b32_e32 v2, 0
508508
; GFX940-NEXT: s_waitcnt vmcnt(0)
509-
; GFX940-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
509+
; GFX940-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
510510
; GFX940-NEXT: s_endpgm
511511
main_body:
512512
%ret = call double @llvm.amdgcn.struct.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i32 0, i32 2)

‎llvm/test/CodeGen/AMDGPU/flat-scratch.ll

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -101,10 +101,10 @@ define amdgpu_kernel void @zero_init_kernel() {
101101
; GFX940-NEXT: s_mov_b32 s3, s0
102102
; GFX940-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
103103
; GFX940-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
104-
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:52
105-
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:36
106-
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:20
107-
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:4
104+
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:52 sc0 sc1
105+
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:36 sc0 sc1
106+
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:20 sc0 sc1
107+
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:4 sc0 sc1
108108
; GFX940-NEXT: s_endpgm
109109
;
110110
; GFX1010-PAL-LABEL: zero_init_kernel:
@@ -265,10 +265,10 @@ define void @zero_init_foo() {
265265
; GFX940-NEXT: s_mov_b32 s3, s0
266266
; GFX940-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
267267
; GFX940-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
268-
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:48
269-
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:32
270-
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:16
271-
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], s32
268+
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:48 sc0 sc1
269+
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:32 sc0 sc1
270+
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:16 sc0 sc1
271+
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], s32 sc0 sc1
272272
; GFX940-NEXT: s_waitcnt vmcnt(0)
273273
; GFX940-NEXT: s_setpc_b64 s[30:31]
274274
;
@@ -860,7 +860,7 @@ define void @private_ptr_foo(ptr addrspace(5) nocapture %arg) {
860860
; GFX940-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
861861
; GFX940-NEXT: v_add_u32_e32 v0, 4, v0
862862
; GFX940-NEXT: v_mov_b32_e32 v1, 0x41200000
863-
; GFX940-NEXT: scratch_store_dword v0, v1, off
863+
; GFX940-NEXT: scratch_store_dword v0, v1, off sc0 sc1
864864
; GFX940-NEXT: s_waitcnt vmcnt(0)
865865
; GFX940-NEXT: s_setpc_b64 s[30:31]
866866
;
@@ -992,10 +992,10 @@ define amdgpu_kernel void @zero_init_small_offset_kernel() {
992992
; GFX940-NEXT: s_mov_b32 s3, s0
993993
; GFX940-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
994994
; GFX940-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
995-
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:260
996-
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:276
997-
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:292
998-
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:308
995+
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:260 sc0 sc1
996+
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:276 sc0 sc1
997+
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:292 sc0 sc1
998+
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:308 sc0 sc1
999999
; GFX940-NEXT: s_endpgm
10001000
;
10011001
; GFX1010-PAL-LABEL: zero_init_small_offset_kernel:
@@ -1176,10 +1176,10 @@ define void @zero_init_small_offset_foo() {
11761176
; GFX940-NEXT: s_mov_b32 s3, s0
11771177
; GFX940-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
11781178
; GFX940-NEXT: v_mov_b64_e32 v[2:3], s[2:3]
1179-
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:256
1180-
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:272
1181-
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:288
1182-
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:304
1179+
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:256 sc0 sc1
1180+
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:272 sc0 sc1
1181+
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:288 sc0 sc1
1182+
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:304 sc0 sc1
11831183
; GFX940-NEXT: s_waitcnt vmcnt(0)
11841184
; GFX940-NEXT: s_setpc_b64 s[30:31]
11851185
;
@@ -2012,10 +2012,10 @@ define amdgpu_kernel void @zero_init_large_offset_kernel() {
20122012
; GFX940-NEXT: s_movk_i32 s0, 0x4004
20132013
; GFX940-NEXT: s_movk_i32 vcc_lo, 0x4004
20142014
; GFX940-NEXT: s_movk_i32 vcc_hi, 0x4004
2015-
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], s1
2016-
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:16
2017-
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:32
2018-
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:48
2015+
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], s1 sc0 sc1
2016+
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:16 sc0 sc1
2017+
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:32 sc0 sc1
2018+
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:48 sc0 sc1
20192019
; GFX940-NEXT: s_endpgm
20202020
;
20212021
; GFX1010-PAL-LABEL: zero_init_large_offset_kernel:
@@ -2224,10 +2224,10 @@ define void @zero_init_large_offset_foo() {
22242224
; GFX940-NEXT: s_add_i32 s0, s32, 0x4004
22252225
; GFX940-NEXT: s_add_i32 vcc_lo, s32, 0x4004
22262226
; GFX940-NEXT: s_add_i32 vcc_hi, s32, 0x4004
2227-
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], s1
2228-
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:16
2229-
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:32
2230-
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:48
2227+
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], s1 sc0 sc1
2228+
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], s0 offset:16 sc0 sc1
2229+
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:32 sc0 sc1
2230+
; GFX940-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:48 sc0 sc1
22312231
; GFX940-NEXT: s_waitcnt vmcnt(0)
22322232
; GFX940-NEXT: s_setpc_b64 s[30:31]
22332233
;

‎llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@ define amdgpu_ps void @buffer_atomic_add_rtn_f64(<4 x i32> inreg %rsrc, double %
5757
; GFX940: ; %bb.0: ; %main_body
5858
; GFX940-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[0:3], 0 idxen sc0
5959
; GFX940-NEXT: s_waitcnt vmcnt(0)
60-
; GFX940-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
60+
; GFX940-NEXT: flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
6161
; GFX940-NEXT: s_endpgm
6262
main_body:
6363
%ret = call double @llvm.amdgcn.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
@@ -93,7 +93,7 @@ define amdgpu_kernel void @buffer_atomic_add_rtn_f64_off4_slc(<4 x i32> inreg %r
9393
; GFX940-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[4:7], 0 idxen offset:4 sc0 nt
9494
; GFX940-NEXT: v_mov_b32_e32 v2, 0
9595
; GFX940-NEXT: s_waitcnt vmcnt(0)
96-
; GFX940-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
96+
; GFX940-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
9797
; GFX940-NEXT: s_endpgm
9898
main_body:
9999
%ret = call double @llvm.amdgcn.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i1 1)
@@ -140,7 +140,7 @@ define amdgpu_ps void @raw_buffer_atomic_add_rtn_f64(<4 x i32> inreg %rsrc, doub
140140
; GFX940: ; %bb.0: ; %main_body
141141
; GFX940-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[0:3], 0 offen sc0
142142
; GFX940-NEXT: s_waitcnt vmcnt(0)
143-
; GFX940-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
143+
; GFX940-NEXT: flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
144144
; GFX940-NEXT: s_endpgm
145145
main_body:
146146
%ret = call double @llvm.amdgcn.raw.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
@@ -176,7 +176,7 @@ define amdgpu_kernel void @raw_buffer_atomic_add_rtn_f64_off4_slc(<4 x i32> inre
176176
; GFX940-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[4:7], 4 offen sc0 nt
177177
; GFX940-NEXT: v_mov_b32_e32 v2, 0
178178
; GFX940-NEXT: s_waitcnt vmcnt(0)
179-
; GFX940-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
179+
; GFX940-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
180180
; GFX940-NEXT: s_endpgm
181181
main_body:
182182
%ret = call double @llvm.amdgcn.raw.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i32 2)
@@ -223,7 +223,7 @@ define amdgpu_ps void @struct_buffer_atomic_add_rtn_f64(<4 x i32> inreg %rsrc, d
223223
; GFX940: ; %bb.0: ; %main_body
224224
; GFX940-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[0:3], 0 idxen sc0
225225
; GFX940-NEXT: s_waitcnt vmcnt(0)
226-
; GFX940-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
226+
; GFX940-NEXT: flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
227227
; GFX940-NEXT: s_endpgm
228228
main_body:
229229
%ret = call double @llvm.amdgcn.struct.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
@@ -259,7 +259,7 @@ define amdgpu_kernel void @struct_buffer_atomic_add_rtn_f64_off4_slc(<4 x i32> i
259259
; GFX940-NEXT: buffer_atomic_add_f64 v[0:1], v2, s[4:7], 0 idxen offset:4 sc0 nt
260260
; GFX940-NEXT: v_mov_b32_e32 v2, 0
261261
; GFX940-NEXT: s_waitcnt vmcnt(0)
262-
; GFX940-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
262+
; GFX940-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
263263
; GFX940-NEXT: s_endpgm
264264
main_body:
265265
%ret = call double @llvm.amdgcn.struct.buffer.atomic.fadd.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i32 0, i32 2)
@@ -306,7 +306,7 @@ define amdgpu_ps void @raw_buffer_atomic_min_rtn_f64(<4 x i32> inreg %rsrc, doub
306306
; GFX940: ; %bb.0: ; %main_body
307307
; GFX940-NEXT: buffer_atomic_min_f64 v[0:1], v2, s[0:3], 0 offen sc0
308308
; GFX940-NEXT: s_waitcnt vmcnt(0)
309-
; GFX940-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
309+
; GFX940-NEXT: flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
310310
; GFX940-NEXT: s_endpgm
311311
main_body:
312312
%ret = call double @llvm.amdgcn.raw.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
@@ -342,7 +342,7 @@ define amdgpu_kernel void @raw_buffer_atomic_min_rtn_f64_off4_slc(<4 x i32> inre
342342
; GFX940-NEXT: buffer_atomic_min_f64 v[0:1], v2, s[4:7], 4 offen sc0 nt
343343
; GFX940-NEXT: v_mov_b32_e32 v2, 0
344344
; GFX940-NEXT: s_waitcnt vmcnt(0)
345-
; GFX940-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
345+
; GFX940-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
346346
; GFX940-NEXT: s_endpgm
347347
main_body:
348348
%ret = call double @llvm.amdgcn.raw.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i32 2)
@@ -389,7 +389,7 @@ define amdgpu_ps void @struct_buffer_atomic_min_rtn_f64(<4 x i32> inreg %rsrc, d
389389
; GFX940: ; %bb.0: ; %main_body
390390
; GFX940-NEXT: buffer_atomic_min_f64 v[0:1], v2, s[0:3], 0 idxen sc0
391391
; GFX940-NEXT: s_waitcnt vmcnt(0)
392-
; GFX940-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
392+
; GFX940-NEXT: flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
393393
; GFX940-NEXT: s_endpgm
394394
main_body:
395395
%ret = call double @llvm.amdgcn.struct.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
@@ -425,7 +425,7 @@ define amdgpu_kernel void @struct_buffer_atomic_min_rtn_f64_off4_slc(<4 x i32> i
425425
; GFX940-NEXT: buffer_atomic_min_f64 v[0:1], v2, s[4:7], 0 idxen offset:4 sc0 nt
426426
; GFX940-NEXT: v_mov_b32_e32 v2, 0
427427
; GFX940-NEXT: s_waitcnt vmcnt(0)
428-
; GFX940-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
428+
; GFX940-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
429429
; GFX940-NEXT: s_endpgm
430430
main_body:
431431
%ret = call double @llvm.amdgcn.struct.buffer.atomic.fmin.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i32 0, i32 2)
@@ -472,7 +472,7 @@ define amdgpu_ps void @raw_buffer_atomic_max_rtn_f64(<4 x i32> inreg %rsrc, doub
472472
; GFX940: ; %bb.0: ; %main_body
473473
; GFX940-NEXT: buffer_atomic_max_f64 v[0:1], v2, s[0:3], 0 offen sc0
474474
; GFX940-NEXT: s_waitcnt vmcnt(0)
475-
; GFX940-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
475+
; GFX940-NEXT: flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
476476
; GFX940-NEXT: s_endpgm
477477
main_body:
478478
%ret = call double @llvm.amdgcn.raw.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0)
@@ -508,7 +508,7 @@ define amdgpu_kernel void @raw_buffer_atomic_max_rtn_f64_off4_slc(<4 x i32> inre
508508
; GFX940-NEXT: buffer_atomic_max_f64 v[0:1], v2, s[4:7], 4 offen sc0 nt
509509
; GFX940-NEXT: v_mov_b32_e32 v2, 0
510510
; GFX940-NEXT: s_waitcnt vmcnt(0)
511-
; GFX940-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
511+
; GFX940-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
512512
; GFX940-NEXT: s_endpgm
513513
main_body:
514514
%ret = call double @llvm.amdgcn.raw.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i32 2)
@@ -555,7 +555,7 @@ define amdgpu_ps void @struct_buffer_atomic_max_rtn_f64(<4 x i32> inreg %rsrc, d
555555
; GFX940: ; %bb.0: ; %main_body
556556
; GFX940-NEXT: buffer_atomic_max_f64 v[0:1], v2, s[0:3], 0 idxen sc0
557557
; GFX940-NEXT: s_waitcnt vmcnt(0)
558-
; GFX940-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
558+
; GFX940-NEXT: flat_store_dwordx2 v[0:1], v[0:1] sc0 sc1
559559
; GFX940-NEXT: s_endpgm
560560
main_body:
561561
%ret = call double @llvm.amdgcn.struct.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i32 0, i32 0)
@@ -591,7 +591,7 @@ define amdgpu_kernel void @struct_buffer_atomic_max_rtn_f64_off4_slc(<4 x i32> i
591591
; GFX940-NEXT: buffer_atomic_max_f64 v[0:1], v2, s[4:7], 0 idxen offset:4 sc0 nt
592592
; GFX940-NEXT: v_mov_b32_e32 v2, 0
593593
; GFX940-NEXT: s_waitcnt vmcnt(0)
594-
; GFX940-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
594+
; GFX940-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9] sc0 sc1
595595
; GFX940-NEXT: s_endpgm
596596
main_body:
597597
%ret = call double @llvm.amdgcn.struct.buffer.atomic.fmax.f64(double %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i32 0, i32 2)

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