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Sjoerd Meijer
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[AArch64] Add CPU Cortex-R82
This adds support for -mcpu=cortex-r82. Some more information about this core can be found here: https://www.arm.com/products/silicon-ip-cpu/cortex-r/cortex-r82 One note about the system register: that is a bit of a refactoring because of small differences between v8.4-A AArch64 and v8-R AArch64. This is based on patches from Mark Murray and Mikhail Maltsev. Differential Revision: https://reviews.llvm.org/D88660
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‎clang/lib/Basic/Targets/AArch64.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -481,6 +481,8 @@ bool AArch64TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
481481
ArchKind = llvm::AArch64::ArchKind::ARMV8_5A;
482482
if (Feature == "+v8.6a")
483483
ArchKind = llvm::AArch64::ArchKind::ARMV8_6A;
484+
if (Feature == "+v8r")
485+
ArchKind = llvm::AArch64::ArchKind::ARMV8R;
484486
if (Feature == "+fullfp16")
485487
HasFullFP16 = true;
486488
if (Feature == "+dotprod")

‎clang/lib/Driver/ToolChains/Arch/AArch64.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -306,7 +306,8 @@ void aarch64::getAArch64TargetFeatures(const Driver &D,
306306
NoCrypto = true;
307307
}
308308

309-
if (std::find(ItBegin, ItEnd, "+v8.4a") != ItEnd) {
309+
if (std::find(ItBegin, ItEnd, "+v8.4a") != ItEnd ||
310+
std::find(ItBegin, ItEnd, "+v8r") != ItEnd) {
310311
if (HasCrypto && !NoCrypto) {
311312
// Check if we have NOT disabled an algorithm with something like:
312313
// +crypto, -algorithm

‎clang/test/Driver/aarch64-cpus.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -178,6 +178,9 @@
178178
// RUN: %clang -target aarch64 -mcpu=cortex-a78 -### -c %s 2>&1 | FileCheck -check-prefix=CORTEXA78 %s
179179
// CORTEXA78: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-a78"
180180

181+
// RUN: %clang -target aarch64 -mcpu=cortex-r82 -### -c %s 2>&1 | FileCheck -check-prefix=CORTEXR82 %s
182+
// CORTEXR82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "cortex-r82"
183+
181184
// RUN: %clang -target aarch64_be -mcpu=exynos-m3 -### -c %s 2>&1 | FileCheck -check-prefix=M3 %s
182185
// RUN: %clang -target aarch64 -mbig-endian -mcpu=exynos-m3 -### -c %s 2>&1 | FileCheck -check-prefix=M3 %s
183186
// RUN: %clang -target aarch64_be -mbig-endian -mcpu=exynos-m3 -### -c %s 2>&1 | FileCheck -check-prefix=M3 %s

‎clang/test/Driver/aarch64-dotprod.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,4 +9,5 @@
99
// RUN: %clang -### -target aarch64 -mcpu=cortex-a75 %s 2>&1 | FileCheck %s
1010
// RUN: %clang -### -target aarch64 -mcpu=cortex-a76 %s 2>&1 | FileCheck %s
1111
// RUN: %clang -### -target aarch64 -mcpu=cortex-a55 %s 2>&1 | FileCheck %s
12+
// RUN: %clang -### -target aarch64 -mcpu=cortex-r82 %s 2>&1 | FileCheck %s
1213
// CHECK: "+dotprod"

‎clang/test/Preprocessor/aarch64-target-features.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -219,6 +219,7 @@
219219
// RUN: %clang -target aarch64 -mcpu=cortex-a57 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-A57 %s
220220
// RUN: %clang -target aarch64 -mcpu=cortex-a72 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-A72 %s
221221
// RUN: %clang -target aarch64 -mcpu=cortex-a73 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-CORTEX-A73 %s
222+
// RUN: %clang -target aarch64 -mcpu=cortex-r82 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-CORTEX-R82 %s
222223
// RUN: %clang -target aarch64 -mcpu=exynos-m3 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-M1 %s
223224
// RUN: %clang -target aarch64 -mcpu=exynos-m4 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-M4 %s
224225
// RUN: %clang -target aarch64 -mcpu=exynos-m5 -### -c %s 2>&1 | FileCheck -check-prefix=CHECK-MCPU-M4 %s
@@ -237,6 +238,7 @@
237238
// CHECK-MCPU-A57: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
238239
// CHECK-MCPU-A72: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
239240
// CHECK-MCPU-CORTEX-A73: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
241+
// CHECK-MCPU-CORTEX-R82: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+v8r" "-target-feature" "+fp-armv8" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" "+dotprod" "-target-feature" "+fp16fml" "-target-feature" "+ras" "-target-feature" "+rdm" "-target-feature" "+rcpc" "-target-feature" "+fullfp16" "-target-feature" "+sm4" "-target-feature" "+sha3" "-target-feature" "+sha2" "-target-feature" "+aes"
240242
// CHECK-MCPU-M1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto"
241243
// CHECK-MCPU-M4: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto" "-target-feature" "+dotprod" "-target-feature" "+fullfp16"
242244
// CHECK-MCPU-KRYO: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-feature" "+neon" "-target-feature" "+crc" "-target-feature" "+crypto"

‎llvm/include/llvm/Support/AArch64TargetParser.def

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,14 @@ AARCH64_ARCH("armv8.6-a", ARMV8_6A, "8.6-A", "v8.6a",
5151
AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD |
5252
AArch64::AEK_SM4 | AArch64::AEK_SHA3 | AArch64::AEK_BF16 |
5353
AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_I8MM))
54+
AARCH64_ARCH("armv8-r", ARMV8R, "8-R", "v8r",
55+
ARMBuildAttrs::CPUArch::v8_R, FK_CRYPTO_NEON_FP_ARMV8,
56+
(AArch64::AEK_CRC | AArch64::AEK_RDM | AArch64::AEK_SSBS |
57+
AArch64::AEK_CRYPTO | AArch64::AEK_SM4 | AArch64::AEK_SHA3 |
58+
AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_DOTPROD |
59+
AArch64::AEK_FP | AArch64::AEK_SIMD | AArch64::AEK_FP16 |
60+
AArch64::AEK_FP16FML | AArch64::AEK_RAS | AArch64::AEK_RCPC |
61+
AArch64::AEK_SB))
5462
#undef AARCH64_ARCH
5563

5664
#ifndef AARCH64_ARCH_EXT_NAME
@@ -130,6 +138,8 @@ AARCH64_CPU_NAME("cortex-a77", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
130138
AARCH64_CPU_NAME("cortex-a78", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
131139
(AArch64::AEK_FP16 | AArch64::AEK_DOTPROD | AArch64::AEK_RCPC |
132140
AArch64::AEK_SSBS))
141+
AARCH64_CPU_NAME("cortex-r82", ARMV8R, FK_CRYPTO_NEON_FP_ARMV8, false,
142+
(AArch64::AEK_NONE))
133143
AARCH64_CPU_NAME("cortex-x1", ARMV8_2A, FK_CRYPTO_NEON_FP_ARMV8, false,
134144
(AArch64::AEK_FP16 | AArch64::AEK_DOTPROD | AArch64::AEK_RCPC |
135145
AArch64::AEK_SSBS))

‎llvm/lib/Support/AArch64TargetParser.cpp

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -118,6 +118,8 @@ bool AArch64::getArchFeatures(AArch64::ArchKind AK,
118118
Features.push_back("+v8.5a");
119119
if (AK == AArch64::ArchKind::ARMV8_6A)
120120
Features.push_back("+v8.6a");
121+
if(AK == AArch64::ArchKind::ARMV8R)
122+
Features.push_back("+v8r");
121123

122124
return AK != ArchKind::INVALID;
123125
}

‎llvm/lib/Target/AArch64/AArch64.td

Lines changed: 30 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -72,9 +72,11 @@ def FeatureLOR : SubtargetFeature<
7272
"lor", "HasLOR", "true",
7373
"Enables ARM v8.1 Limited Ordering Regions extension">;
7474

75-
def FeatureVH : SubtargetFeature<
76-
"vh", "HasVH", "true",
77-
"Enables ARM v8.1 Virtual Host extension">;
75+
def FeatureCONTEXTIDREL2 : SubtargetFeature<"CONTEXTIDREL2", "HasCONTEXTIDREL2",
76+
"true", "Enable RW operand CONTEXTIDR_EL2" >;
77+
78+
def FeatureVH : SubtargetFeature<"vh", "HasVH", "true",
79+
"Enables ARM v8.1 Virtual Host extension", [FeatureCONTEXTIDREL2] >;
7880

7981
def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
8082
"Enable ARMv8 PMUv3 Performance Monitors extension">;
@@ -441,6 +443,22 @@ def HasV8_6aOps : SubtargetFeature<
441443
[HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps,
442444
FeatureEnhancedCounterVirtualization, FeatureMatMulInt8]>;
443445

446+
def HasV8_0rOps : SubtargetFeature<
447+
"v8r", "HasV8_0rOps", "true", "Support ARM v8r instructions",
448+
[//v8.1
449+
FeatureCRC, FeaturePAN, FeatureRDM, FeatureLSE, FeatureCONTEXTIDREL2,
450+
//v8.2
451+
FeaturePerfMon, FeatureRAS, FeaturePsUAO, FeatureSM4,
452+
FeatureSHA3, FeatureCCPP, FeatureFullFP16, FeaturePAN_RWV,
453+
//v8.3
454+
FeatureComplxNum, FeatureCCIDX, FeatureJS,
455+
FeaturePA, FeatureRCPC,
456+
//v8.4
457+
FeatureDotProd, FeatureFP16FML, FeatureRASv8_4, FeatureTRACEV8_4,
458+
FeatureTLB_RMI, FeatureFMI, FeatureDIT, FeatureSEL2, FeatureRCPC_IMMO,
459+
//v8.5
460+
FeatureSSBS, FeaturePredRes, FeatureSB, FeatureSpecRestrict]>;
461+
444462
//===----------------------------------------------------------------------===//
445463
// Register File Description
446464
//===----------------------------------------------------------------------===//
@@ -506,6 +524,7 @@ def PAUnsupported : AArch64Unsupported {
506524
}
507525

508526
include "AArch64SchedA53.td"
527+
include "AArch64SchedA55.td"
509528
include "AArch64SchedA57.td"
510529
include "AArch64SchedCyclone.td"
511530
include "AArch64SchedFalkor.td"
@@ -652,6 +671,13 @@ def ProcA78 : SubtargetFeature<"cortex-a78", "ARMProcFamily",
652671
FeatureSSBS,
653672
FeatureDotProd]>;
654673

674+
def ProcR82 : SubtargetFeature<"cortex-r82", "ARMProcFamily",
675+
"CortexR82",
676+
"Cortex-R82 ARM Processors", [
677+
// All features are implied by v8_0r ops:
678+
HasV8_0rOps,
679+
]>;
680+
655681
def ProcX1 : SubtargetFeature<"cortex-x1", "ARMProcFamily", "CortexX1",
656682
"Cortex-X1 ARM processors", [
657683
HasV8_2aOps,
@@ -1013,6 +1039,7 @@ def : ProcessorModel<"cortex-a76", CortexA57Model, [ProcA76]>;
10131039
def : ProcessorModel<"cortex-a76ae", CortexA57Model, [ProcA76]>;
10141040
def : ProcessorModel<"cortex-a77", CortexA57Model, [ProcA77]>;
10151041
def : ProcessorModel<"cortex-a78", CortexA57Model, [ProcA78]>;
1042+
def : ProcessorModel<"cortex-r82", CortexA55Model, [ProcR82]>;
10161043
def : ProcessorModel<"cortex-x1", CortexA57Model, [ProcX1]>;
10171044
def : ProcessorModel<"neoverse-e1", CortexA53Model, [ProcNeoverseE1]>;
10181045
def : ProcessorModel<"neoverse-n1", CortexA57Model, [ProcNeoverseN1]>;

‎llvm/lib/Target/AArch64/AArch64Subtarget.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -103,6 +103,7 @@ void AArch64Subtarget::initializeProperties() {
103103
case CortexA76:
104104
case CortexA77:
105105
case CortexA78:
106+
case CortexR82:
106107
case CortexX1:
107108
PrefFunctionLogAlignment = 4;
108109
break;

‎llvm/lib/Target/AArch64/AArch64Subtarget.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -57,6 +57,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
5757
CortexA76,
5858
CortexA77,
5959
CortexA78,
60+
CortexR82,
6061
CortexX1,
6162
ExynosM3,
6263
Falkor,
@@ -84,6 +85,9 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
8485
bool HasV8_5aOps = false;
8586
bool HasV8_6aOps = false;
8687

88+
bool HasV8_0rOps = false;
89+
bool HasCONTEXTIDREL2 = false;
90+
8791
bool HasFPARMv8 = false;
8892
bool HasNEON = false;
8993
bool HasCrypto = false;
@@ -306,6 +310,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
306310
bool hasV8_3aOps() const { return HasV8_3aOps; }
307311
bool hasV8_4aOps() const { return HasV8_4aOps; }
308312
bool hasV8_5aOps() const { return HasV8_5aOps; }
313+
bool hasV8_0rOps() const { return HasV8_0rOps; }
309314

310315
bool hasZeroCycleRegMove() const { return HasZeroCycleRegMove; }
311316

@@ -343,6 +348,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
343348
bool hasSHA3() const { return HasSHA3; }
344349
bool hasSHA2() const { return HasSHA2; }
345350
bool hasAES() const { return HasAES; }
351+
bool hasCONTEXTIDREL2() const { return HasCONTEXTIDREL2; }
346352
bool balanceFPOps() const { return BalanceFPOps; }
347353
bool predictableSelectIsExpensive() const {
348354
return PredictableSelectIsExpensive;

‎llvm/lib/Target/AArch64/AArch64SystemOperands.td

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,11 @@ def HasPAN_RWV : Predicate<"Subtarget->hasPAN_RWV()">,
3232
AssemblerPredicate<(all_of FeaturePAN_RWV),
3333
"ARM v8.2 PAN AT S1E1R and AT S1E1W Variation">;
3434

35+
def HasCONTEXTIDREL2
36+
: Predicate<"Subtarget->hasCONTEXTIDREL2()">,
37+
AssemblerPredicate<(all_of FeatureCONTEXTIDREL2),
38+
"Target contains CONTEXTIDR_EL2 RW operand">;
39+
3540
//===----------------------------------------------------------------------===//
3641
// AT (address translate) instruction options.
3742
//===----------------------------------------------------------------------===//
@@ -1220,7 +1225,6 @@ def : RWSysReg<"LORC_EL1", 0b11, 0b000, 0b1010, 0b0100, 0b011>;
12201225
// Op0 Op1 CRn CRm Op2
12211226
let Requires = [{ {AArch64::FeatureVH} }] in {
12221227
def : RWSysReg<"TTBR1_EL2", 0b11, 0b100, 0b0010, 0b0000, 0b001>;
1223-
def : RWSysReg<"CONTEXTIDR_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b001>;
12241228
def : RWSysReg<"CNTHV_TVAL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b000>;
12251229
def : RWSysReg<"CNTHV_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b010>;
12261230
def : RWSysReg<"CNTHV_CTL_EL2", 0b11, 0b100, 0b1110, 0b0011, 0b001>;
@@ -1246,6 +1250,9 @@ def : RWSysReg<"CNTV_CTL_EL02", 0b11, 0b101, 0b1110, 0b0011, 0b001>;
12461250
def : RWSysReg<"CNTV_CVAL_EL02", 0b11, 0b101, 0b1110, 0b0011, 0b010>;
12471251
def : RWSysReg<"SPSR_EL12", 0b11, 0b101, 0b0100, 0b0000, 0b000>;
12481252
def : RWSysReg<"ELR_EL12", 0b11, 0b101, 0b0100, 0b0000, 0b001>;
1253+
let Requires = [{ {AArch64::FeatureCONTEXTIDREL2} }] in {
1254+
def : RWSysReg<"CONTEXTIDR_EL2", 0b11, 0b100, 0b1101, 0b0000, 0b001>;
1255+
}
12491256
}
12501257
// v8.2a registers
12511258
// Op0 Op1 CRn CRm Op2

‎llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5251,6 +5251,7 @@ static void ExpandCryptoAEK(AArch64::ArchKind ArchKind,
52515251
case AArch64::ArchKind::ARMV8_4A:
52525252
case AArch64::ArchKind::ARMV8_5A:
52535253
case AArch64::ArchKind::ARMV8_6A:
5254+
case AArch64::ArchKind::ARMV8R:
52545255
RequestedExtensions.push_back("sm4");
52555256
RequestedExtensions.push_back("sha3");
52565257
RequestedExtensions.push_back("sha2");

‎llvm/unittests/Support/TargetParserTest.cpp

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -881,6 +881,14 @@ TEST(TargetParserTest, testAArch64CPU) {
881881
AArch64::AEK_LSE | AArch64::AEK_FP16 | AArch64::AEK_DOTPROD |
882882
AArch64::AEK_RCPC | AArch64::AEK_SSBS,
883883
"8.2-A"));
884+
EXPECT_TRUE(testAArch64CPU(
885+
"cortex-r82", "armv8-r", "crypto-neon-fp-armv8",
886+
AArch64::AEK_CRC | AArch64::AEK_RDM | AArch64::AEK_SSBS |
887+
AArch64::AEK_CRYPTO | AArch64::AEK_SM4 | AArch64::AEK_SHA3 |
888+
AArch64::AEK_SHA2 | AArch64::AEK_AES | AArch64::AEK_DOTPROD |
889+
AArch64::AEK_FP | AArch64::AEK_SIMD | AArch64::AEK_FP16 |
890+
AArch64::AEK_FP16FML | AArch64::AEK_RAS | AArch64::AEK_RCPC |
891+
AArch64::AEK_SB, "8-R"));
884892
EXPECT_TRUE(testAArch64CPU(
885893
"cortex-x1", "armv8.2-a", "crypto-neon-fp-armv8",
886894
AArch64::AEK_CRC | AArch64::AEK_CRYPTO | AArch64::AEK_FP |
@@ -1026,7 +1034,7 @@ TEST(TargetParserTest, testAArch64CPU) {
10261034
"8.2-A"));
10271035
}
10281036

1029-
static constexpr unsigned NumAArch64CPUArchs = 42;
1037+
static constexpr unsigned NumAArch64CPUArchs = 43;
10301038

10311039
TEST(TargetParserTest, testAArch64CPUArchList) {
10321040
SmallVector<StringRef, NumAArch64CPUArchs> List;

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