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AMDGPU/GlobalISel: Prepare some tests for store selection
Mostsly these would fail due to trying to use SI with a flat operation. Implementing global loads with MUBUF is more work than flat, so these won't be handled in the initial load selection. Others fail because store of s64 won't initially work, as the current set of patterns expect everything to be turned into v2i32. llvm-svn: 365493
1 parent dbb6d01 commit fdd761a

17 files changed

+92
-124
lines changed

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir

Lines changed: 5 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,4 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
12
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
23
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
34
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
@@ -11,27 +12,25 @@ body: |
1112
bb.0:
1213
liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr3_vgpr4
1314
15+
1416
; GFX6-LABEL: name: add_s32
1517
; GFX6: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
1618
; GFX6: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
1719
; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
18-
; GFX6: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
1920
; GFX6: [[S_ADD_U32_:%[0-9]+]]:sreg_32_xm0 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
2021
; GFX6: %7:vgpr_32, dead %12:sreg_64_xexec = V_ADD_I32_e64 [[COPY2]], [[S_ADD_U32_]], 0, implicit $exec
2122
; GFX6: %8:vgpr_32, dead %11:sreg_64_xexec = V_ADD_I32_e64 [[S_ADD_U32_]], %7, 0, implicit $exec
2223
; GFX6: %9:vgpr_32, dead %10:sreg_64_xexec = V_ADD_I32_e64 %8, [[COPY2]], 0, implicit $exec
23-
; GFX6: FLAT_STORE_DWORD [[COPY3]], %9, 0, 0, 0, 0, implicit $exec, implicit $flat_scr
24+
; GFX6: S_ENDPGM 0, implicit %9
2425
; GFX9-LABEL: name: add_s32
2526
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
2627
; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
2728
; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0
28-
; GFX9: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
2929
; GFX9: [[S_ADD_U32_:%[0-9]+]]:sreg_32_xm0 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
3030
; GFX9: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY2]], [[S_ADD_U32_]], 0, implicit $exec
3131
; GFX9: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_ADD_U32_]], [[V_ADD_U32_e64_]], 0, implicit $exec
3232
; GFX9: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_1]], [[COPY2]], 0, implicit $exec
33-
; GFX9: FLAT_STORE_DWORD [[COPY3]], [[V_ADD_U32_e64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
34-
33+
; GFX9: S_ENDPGM 0, implicit [[V_ADD_U32_e64_2]]
3534
%0:sgpr(s32) = COPY $sgpr0
3635
%1:sgpr(s32) = COPY $sgpr1
3736
%2:vgpr(s32) = COPY $vgpr0
@@ -51,6 +50,6 @@ body: |
5150
; add vv
5251
%9:vgpr(s32) = G_ADD %8, %2
5352
54-
G_STORE %9, %3 :: (store 4, addrspace 1)
53+
S_ENDPGM 0, implicit %9
5554
5655
...

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir

Lines changed: 3 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,6 @@
1-
# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
2-
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
1+
# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
2+
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
33

4-
--- |
5-
define void @cvt_pkrtz(i32 addrspace(1)* %global0) { ret void }
6-
...
74
---
85

96
name: cvt_pkrtz
@@ -38,8 +35,5 @@ body: |
3835
%7:vgpr(s32) = G_BITCAST %4
3936
%8:vgpr(s32) = G_BITCAST %5
4037
%9:vgpr(s32) = G_BITCAST %6
41-
G_STORE %7, %3 :: (store 4 into %ir.global0, addrspace 1)
42-
G_STORE %8, %3 :: (store 4 into %ir.global0, addrspace 1)
43-
G_STORE %9, %3 :: (store 4 into %ir.global0, addrspace 1)
38+
S_ENDPGM 0, implicit %7, implicit %8, implicit %9
4439
...
45-
---

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir

Lines changed: 3 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,6 @@
1-
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN,SI
2-
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN,VI
1+
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN,SI
2+
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN,VI
33

4-
--- |
5-
define void @ashr(i32 addrspace(1)* %global0) {ret void}
6-
...
74
---
85

96
name: ashr
@@ -80,7 +77,6 @@ body: |
8077
%17:vgpr(s32) = G_ASHR %16, %5
8178
8279
83-
G_STORE %17, %3 :: (store 4 into %ir.global0, addrspace 1)
80+
S_ENDPGM 0, implicit %17
8481
8582
...
86-
---

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitcast.mir

Lines changed: 7 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1,26 +1,21 @@
1-
# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
1+
# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN
22

3-
--- |
4-
define amdgpu_kernel void @bitcast(i32 addrspace(1)* %global0) {ret void}
5-
...
63
---
74

85
name: bitcast
96
legalized: true
107
regBankSelected: true
8+
tracksRegLiveness: true
119

1210
# GCN-LABEL: name: bitcast
1311
# GCN: [[A:%[0-9]+]]:vgpr_32 = COPY $vgpr0
14-
# GCN: [[B:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
15-
# GCN: FLAT_STORE_DWORD [[B]], [[A]]
12+
# GCN: S_ENDPGM 0, implicit [[A]]
1613

1714
body: |
1815
bb.0:
19-
liveins: $sgpr0, $vgpr3_vgpr4
16+
liveins: $vgpr0
2017
%0:vgpr(s32) = COPY $vgpr0
21-
%1:vgpr(p1) = COPY $vgpr3_vgpr4
22-
%2:vgpr(<2 x s16>) = G_BITCAST %0
23-
%3:vgpr(s32) = G_BITCAST %2
24-
G_STORE %3, %1 :: (store 4 into %ir.global0, addrspace 1)
18+
%1:vgpr(<2 x s16>) = G_BITCAST %0
19+
%2:vgpr(s32) = G_BITCAST %1
20+
S_ENDPGM 0, implicit %2
2521
...
26-
---

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir

Lines changed: 4 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,5 @@
1-
# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
1+
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
22

3-
--- |
4-
define amdgpu_kernel void @constant(i32 addrspace(1)* %global0, i64 addrspace(1)* %global1) {ret void}
5-
...
63
---
74

85
name: constant
@@ -49,13 +46,7 @@ body: |
4946
; GCN: %{{[0-9]+}}:vreg_64 = REG_SEQUENCE [[LO3]], %subreg.sub0, [[HI3]], %subreg.sub1
5047
%9:vgpr(s64) = G_FCONSTANT double 1.0
5148
52-
G_STORE %2, %0 :: (volatile store 4 into %ir.global0, addrspace 1)
53-
G_STORE %4, %0 :: (volatile store 4 into %ir.global0, addrspace 1)
54-
G_STORE %6, %0 :: (volatile store 4 into %ir.global0, addrspace 1)
55-
G_STORE %8, %0 :: (volatile store 4 into %ir.global0, addrspace 1)
56-
G_STORE %3, %1 :: (volatile store 8 into %ir.global1, addrspace 1)
57-
G_STORE %5, %1 :: (volatile store 8 into %ir.global1, addrspace 1)
58-
G_STORE %7, %1 :: (volatile store 8 into %ir.global1, addrspace 1)
59-
G_STORE %9, %1 :: (volatile store 8 into %ir.global1, addrspace 1)
49+
S_ENDPGM 0, implicit %2, implicit %4, implicit %6, implicit %8, implicit %3, implicit %5, implicit %7, implicit %9
50+
6051
...
61-
---
52+

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir

Lines changed: 23 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel -o - %s | FileCheck -check-prefix=WAVE64 %s
3-
# RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -run-pass=instruction-select -verify-machineinstrs -global-isel -o - %s | FileCheck -check-prefix=WAVE32 %s
2+
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=WAVE64 %s
3+
# RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=+wavefrontsize32,-wavefrontsize64 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=WAVE32 %s
44

55
---
66

@@ -151,6 +151,13 @@ body: |
151151
; GCN-LABEL: name: copy_sgpr_no_type
152152
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
153153
; GCN: S_ENDPGM 0, implicit [[COPY]]
154+
; WAVE64-LABEL: name: copy_sgpr_no_type
155+
; WAVE64: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
156+
; WAVE64: S_ENDPGM 0, implicit [[COPY]]
157+
; WAVE32-LABEL: name: copy_sgpr_no_type
158+
; WAVE32: $vcc_hi = IMPLICIT_DEF
159+
; WAVE32: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
160+
; WAVE32: S_ENDPGM 0, implicit [[COPY]]
154161
%0:sreg_32_xm0 = COPY $sgpr0
155162
%1:sreg_32_xm0 = COPY %0
156163
S_ENDPGM 0, implicit %1
@@ -170,6 +177,13 @@ body: |
170177
; GCN-LABEL: name: copy_vgpr_no_type
171178
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
172179
; GCN: S_ENDPGM 0, implicit [[COPY]]
180+
; WAVE64-LABEL: name: copy_vgpr_no_type
181+
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
182+
; WAVE64: S_ENDPGM 0, implicit [[COPY]]
183+
; WAVE32-LABEL: name: copy_vgpr_no_type
184+
; WAVE32: $vcc_hi = IMPLICIT_DEF
185+
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
186+
; WAVE32: S_ENDPGM 0, implicit [[COPY]]
173187
%0:vgpr_32 = COPY $vgpr0
174188
%1:vgpr_32 = COPY %0
175189
S_ENDPGM 0, implicit %1
@@ -189,6 +203,13 @@ body: |
189203
; GCN-LABEL: name: copy_maybe_vcc
190204
; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
191205
; GCN: S_ENDPGM 0, implicit [[COPY]]
206+
; WAVE64-LABEL: name: copy_maybe_vcc
207+
; WAVE64: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
208+
; WAVE64: S_ENDPGM 0, implicit [[COPY]]
209+
; WAVE32-LABEL: name: copy_maybe_vcc
210+
; WAVE32: $vcc_hi = IMPLICIT_DEF
211+
; WAVE32: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
212+
; WAVE32: S_ENDPGM 0, implicit [[COPY]]
192213
%0:sreg_64_xexec = COPY $sgpr0_sgpr1
193214
%1:sreg_64_xexec = COPY %0
194215
S_ENDPGM 0, implicit %1

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.mir

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,5 @@
1-
# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
1+
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN
22

3-
--- |
4-
define amdgpu_kernel void @fadd(i32 addrspace(1)* %global0) {ret void}
5-
...
63
---
74

85
name: fadd
@@ -30,8 +27,7 @@ body: |
3027
; GCN: V_ADD_F32_e64
3128
%6:vgpr(s32) = G_FADD %1, %2
3229
33-
G_STORE %4, %3 :: (store 4 into %ir.global0)
34-
G_STORE %5, %3 :: (store 4 into %ir.global0)
35-
G_STORE %6, %3 :: (store 4 into %ir.global0)
30+
G_STORE %4, %3 :: (store 4, addrspace 1)
31+
G_STORE %5, %3 :: (store 4, addrspace 1)
32+
G_STORE %6, %3 :: (store 4, addrspace 1)
3633
...
37-
---

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir

Lines changed: 3 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN
2+
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN
33

44
---
55

@@ -53,13 +53,10 @@ body: |
5353
; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr0_sgpr1
5454
; GCN: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
5555
; GCN: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
56-
; GCN: [[COPY3:%[0-9]+]]:vreg_64 = COPY $vgpr4_vgpr5
5756
; GCN: [[V_MUL_F64_:%[0-9]+]]:vreg_64 = V_MUL_F64 0, [[COPY1]], 0, [[COPY]], 0, 0, implicit $exec
5857
; GCN: [[V_MUL_F64_1:%[0-9]+]]:vreg_64 = V_MUL_F64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $exec
5958
; GCN: [[V_MUL_F64_2:%[0-9]+]]:vreg_64 = V_MUL_F64 0, [[COPY1]], 0, [[COPY2]], 0, 0, implicit $exec
60-
; GCN: FLAT_STORE_DWORDX2 [[COPY3]], [[V_MUL_F64_]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
61-
; GCN: FLAT_STORE_DWORDX2 [[COPY3]], [[V_MUL_F64_1]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
62-
; GCN: FLAT_STORE_DWORDX2 [[COPY3]], [[V_MUL_F64_2]], 0, 0, 0, 0, implicit $exec, implicit $flat_scr
59+
; GCN: S_ENDPGM 0, implicit [[V_MUL_F64_]], implicit [[V_MUL_F64_1]], implicit [[V_MUL_F64_2]]
6360
%0:sgpr(s64) = COPY $sgpr0_sgpr1
6461
%1:vgpr(s64) = COPY $vgpr0_vgpr1
6562
%2:vgpr(s64) = COPY $vgpr2_vgpr3
@@ -73,10 +70,8 @@ body: |
7370
7471
; fmul vv
7572
%6:vgpr(s64) = G_FMUL %1, %2
73+
S_ENDPGM 0, implicit %4, implicit %5, implicit %6
7674
77-
G_STORE %4, %3 :: (store 8, addrspace 1)
78-
G_STORE %5, %3 :: (store 8, addrspace 1)
79-
G_STORE %6, %3 :: (store 8, addrspace 1)
8075
...
8176

8277
---

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir

Lines changed: 3 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,5 @@
1-
# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
1+
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefix=GCN
22

3-
--- |
4-
define amdgpu_kernel void @fptoui(i32 addrspace(1)* %global0) {ret void}
5-
...
63
---
74

85
name: fptoui
@@ -30,7 +27,6 @@ body: |
3027
; GCN: V_CVT_U32_F32_e64 0, [[VGPR]], 0, 0
3128
%4:vgpr(s32) = G_FPTOUI %1
3229
33-
G_STORE %3, %2 :: (store 4 into %ir.global0)
34-
G_STORE %4, %2 :: (store 4 into %ir.global0)
30+
G_STORE %3, %2 :: (store 4, addrspace 1)
31+
G_STORE %4, %2 :: (store 4, addrspace 1)
3532
...
36-
---

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
1-
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
2-
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
1+
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN
2+
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN
33

44
---
55
name: icmp_s32_s_mix

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-implicit-def.mir

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefixes=GCN %s
3-
# XUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' -o /dev/null %s 2>&1 | FileCheck -check-prefixes=ERR %s
2+
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefixes=GCN %s
3+
# XUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' -o /dev/null %s 2>&1 | FileCheck -check-prefixes=ERR %s
44

55
# G_IMPLICIT_DEF should probably never be produced for scc. Make sure there's no crash.
66
# ERR: remark: <unknown>:0:0: cannot select: %0:scc(s1) = G_IMPLICIT_DEF (in function: implicit_def_s1_scc)

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-inttoptr.mir

Lines changed: 3 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,5 @@
1-
# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
1+
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN
22

3-
--- |
4-
define amdgpu_kernel void @inttoptr(i32 addrspace(4)* %const0, i32 addrspace(0)* %flat0) {ret void}
5-
...
63
---
74

85
name: inttoptr
@@ -26,9 +23,8 @@ body: |
2623
%0:sgpr(s64) = COPY $sgpr0_sgpr1
2724
%1:vgpr(s64) = COPY $vgpr0_vgpr1
2825
%2:sgpr(p4) = G_INTTOPTR %0
29-
%3:sgpr(s32) = G_LOAD %2 :: (load 4 from %ir.const0)
26+
%3:sgpr(s32) = G_LOAD %2 :: (load 4, addrspace 1)
3027
%4:vgpr(p0) = G_INTTOPTR %1
3128
%5:vgpr(s32) = COPY %3
32-
G_STORE %5, %4 :: (store 4 into %ir.flat0)
29+
G_STORE %5, %4 :: (store 4, addrspace 1)
3330
...
34-
---

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-maxnum.mir

Lines changed: 5 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,5 @@
1-
# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
1+
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN
22

3-
--- |
4-
define void @maxnum(i32 addrspace(1)* %global0) { ret void }
5-
...
63
---
74

85
name: maxnum
@@ -40,9 +37,9 @@ body: |
4037
; GCN: V_MAX_F32_e32 [[VGPR0]], [[VGPR1]]
4138
%6:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.maxnum.f32), %1, %2
4239
43-
G_STORE %4, %3 :: (store 4 into %ir.global0)
44-
G_STORE %5, %3 :: (store 4 into %ir.global0)
45-
G_STORE %6, %3 :: (store 4 into %ir.global0)
40+
G_STORE %4, %3 :: (store 4, addrspace 1)
41+
G_STORE %5, %3 :: (store 4, addrspace 1)
42+
G_STORE %6, %3 :: (store 4, addrspace 1)
4643
4744
; 64-bit
4845
@@ -58,9 +55,6 @@ body: |
5855
; GCN: V_MAX_F64 0, [[VGPR64_0]], 0, [[VGPR64_1]], 0, 0
5956
%16:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.maxnum.f64), %11, %12
6057
61-
G_STORE %14, %3 :: (store 8 into %ir.global0)
62-
G_STORE %15, %3 :: (store 8 into %ir.global0)
63-
G_STORE %16, %3 :: (store 8 into %ir.global0)
58+
S_ENDPGM 0, implicit %14, implicit %15, implicit %16
6459
6560
...
66-
---

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-minnum.mir

Lines changed: 5 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,5 @@
1-
# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
1+
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN
22

3-
--- |
4-
define void @minnum(i32 addrspace(1)* %global0) { ret void }
5-
...
63
---
74

85
name: minnum
@@ -40,9 +37,9 @@ body: |
4037
; GCN: V_MIN_F32_e32 [[VGPR0]], [[VGPR1]]
4138
%6:vgpr(s32) = G_INTRINSIC intrinsic(@llvm.minnum.f32), %1, %2
4239
43-
G_STORE %4, %3 :: (store 4 into %ir.global0)
44-
G_STORE %5, %3 :: (store 4 into %ir.global0)
45-
G_STORE %6, %3 :: (store 4 into %ir.global0)
40+
G_STORE %4, %3 :: (store 4, addrspace 1)
41+
G_STORE %5, %3 :: (store 4, addrspace 1)
42+
G_STORE %6, %3 :: (store 4, addrspace 1)
4643
4744
; 64-bit
4845
@@ -58,8 +55,5 @@ body: |
5855
; GCN: V_MIN_F64 0, [[VGPR64_0]], 0, [[VGPR64_1]], 0, 0
5956
%16:vgpr(s64) = G_INTRINSIC intrinsic(@llvm.minnum.f64), %11, %12
6057
61-
G_STORE %14, %3 :: (store 8 into %ir.global0)
62-
G_STORE %15, %3 :: (store 8 into %ir.global0)
63-
G_STORE %16, %3 :: (store 8 into %ir.global0)
58+
S_ENDPGM 0, implicit %14, implicit %15, implicit %16
6459
...
65-
---

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-or.mir

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,5 @@
1-
# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
1+
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefixes=GCN
22

3-
--- |
4-
define void @or(i32 addrspace(1)* %global0) {ret void}
5-
...
63
---
74

85
name: or
@@ -39,7 +36,6 @@ body: |
3936
; GCN: [[VV:%[0-9]+]]:vgpr_32 = V_OR_B32_e32 [[SV]], [[VGPR0]]
4037
%9:vgpr(s32) = G_OR %8, %2
4138
42-
G_STORE %9, %3 :: (store 4 into %ir.global0, addrspace 1)
39+
G_STORE %9, %3 :: (store 4, addrspace 1)
4340
4441
...
45-
---

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