Typestate #338
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Typestate #338
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Lots of work on typestate_check, seems to get a lot of the way through checking the standard library. * Added for, for_each, assign_op, bind, cast, put, check, break, and cont. (I'm not sure break and cont are actually handled correctly.) * Fixed side-effect bug in seq_preconds so that unioning the preconditions of a sequence of statements or expressions is handled correctly. * Pass poststate correctly through a stmt_decl. * Handle expr_ret and expr_fail properly (after execution of a ret or fail, everything is true -- this is needed to handle ifs and alts where one branch is a ret or fail) * Fixed bug in set_prestate_ann where a thing that needed to be mutated wasn't getting passed as an alias * Fixed bug in how expr_alt was treated (zero is not the identity for intersect, who knew, right?) * Update logging to reflect log_err vs. log * Fixed find_locals so as to return all local decls and exclude function arguments. * Make union_postconds work on an empty vector (needed to handle empty blocks correctly) * Added _vec.cat_options, which takes a list of option[T] to a list of T, ignoring any Nones * Added two test cases.
Added support for self_method, cont, chan, port, recv, send, be, do_while, spawn, and ext; handled break and cont correctly. (However, there are no non-xfailed test cases for ext or spawn in stage0 currently.) Although the standard library compiles and all test cases pass with typestate enabled, I left typestate checking disabled as rustc terminates abnormally when building the standard library if so, even though it does generate code correctly.
(needed for typestate_check). Also changed a (log; fail) to (log_err; fail) in typestate_check, and added some more logging funs in util.common.
kazcw
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Oct 23, 2018
* Prepare portable packed SIMD vector types for RFCs
This commit cleans up the implementation of the Portable Packed Vector Types
(PPTV), adds some new features, and makes some breaking changes.
The implementation is moved to `coresimd/src/ppvt` (they are
still exposed via `coresimd::simd`).
As before, the vector types of a certain width are implemented in the `v{width}`
submodules. The `macros.rs` file has been rewritten as an `api` module that
exposes the macros to implement each API.
It should now hopefully be really clear where each API is implemented, and which types
implement these APIs. It should also now be really clear which APIs are tested and how.
- boolean vectors of the form `b{element_size}x{number_of_lanes}`.
- reductions: arithmetic, bitwise, min/max, and boolean - only the facade,
and a naive working implementation. These need to be implemented
as `llvm.experimental.vector.reduction.{...}` but this needs rustc support first.
- FromBits trait analogous to `{f32,f64}::from_bits` that perform "safe" transmutes.
Instead of writing `From::from`/`x.into()` (see below for breaking changes) now you write
`FromBits::from_bits`/`x.into_bits()`.
- portable vector types implement `Default` and `Hash`
- tests for all portable vector types and all portable operations (~2000 new tests).
- (hopefully) comprehensive implementation of bitwise transmutes and lane-wise
casts (before `From` and the `.as_...` methods where implemented "when they were needed".
- documentation for PPTV (not great yet, but better than nothing)
- conversions/transmutes from/to x86 architecture specific vector types
- `store/load` API has been replaced with `{store,load}_{aligned,unaligned}`
- `eq,ne,lt,le,gt,ge` APIs now return boolean vectors
- The `.as_{...}` methods have been removed. Lane-wise casts are now performed by `From`.
- `From` now perform casts (see above). It used to perform bitwise transmutes.
- `simd` vectors' `replace` method's result is now `#[must_use]`.
* enable backtrace and nocapture
* unalign load/store fail test by 1 byte
* update arm and aarch64 neon modules
* fix arm example
* fmt
* clippy and read example that rustfmt swallowed
* reductions should take self
* rename add/mul -> sum/product; delete other arith reductions
* clean up fmt::LowerHex impl
* revert incorret doc change
* make Hash equivalent to [T; lanes()]
* use travis_wait to increase timeout limit to 20 minutes
* remove travis_wait; did not help
* implement reductions on top of the llvm.experimental.vector.reduction intrinsics
* implement cmp for boolean vectors
* add missing eq impl file
* implement default
* rename llvm intrinsics
* fix aarch64 example error
* replace #[inline(always)] with #[inline]
* remove cargo clean from run.sh
* workaround broken product in aarch64
* make boolean vector constructors const fn
* fix more reductions on aarch64
* fix min/max reductions on aarch64
* remove whitespace
* remove all boolean vector types except for b8xN
* use a sum reduction fallback on aarch64
* disable llvm add reduction for aarch64
* rename the llvm intrinsics to use llvm names
* remove old macros.rs file
dlrobertson
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Nov 29, 2018
Fixups for token ref
Aaron1011
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Oct 26, 2020
Update gimli
ZuseZ4
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Mar 7, 2023
* Handle sret * add tests
carolynzech
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Jun 24, 2025
…g#338) Towards rust-lang#71 These are the changes contributed by [SahithiMV](https://github.com/SahithiMV) in rust-lang#184 plus the proposed changes in that PR. By submitting this pull request, I confirm that my contribution is made under the terms of the Apache 2.0 and MIT licenses. --------- Co-authored-by: aaluna <[email protected]> Co-authored-by: SahithiMV <[email protected]> Co-authored-by: aaluna <[email protected]> Co-authored-by: Carolyn Zech <[email protected]> Co-authored-by: Zyad Hassan <[email protected]> Co-authored-by: Carolyn Zech <[email protected]>
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supersedes all other pull requests