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lu-zerognzlbg
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Add Altivec vec_andc
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crates/core_arch/src/powerpc/altivec.rs

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@@ -337,6 +337,44 @@ mod sealed {
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}
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}
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#[inline]
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#[target_feature(enable = "altivec")]
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#[cfg_attr(all(test, not(target_feature = "vsx")), assert_instr(vandc))]
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#[cfg_attr(all(test, target_feature = "vsx"), assert_instr(xxlandc))]
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unsafe fn andc(a: u8x16, b: u8x16) -> u8x16 {
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simd_and(simd_xor(u8x16::splat(0xff), b), a)
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}
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pub trait VectorAndc<Other> {
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type Result;
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unsafe fn vec_andc(self, b: Other) -> Self::Result;
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}
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macro_rules! impl_vec_andc {
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(($a:ty, $b:ty) -> $r:ty) => {
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impl VectorAndc<$b> for $a {
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type Result = $r;
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#[inline]
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#[target_feature(enable = "altivec")]
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unsafe fn vec_andc(self, b: $b) -> Self::Result {
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transmute(andc(transmute(self), transmute(b)))
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}
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}
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};
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(($a:ty, ~$b:ty) -> $r:ty) => {
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impl_vec_andc! { ($a, $a) -> $r }
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impl_vec_andc! { ($a, $b) -> $r }
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impl_vec_andc! { ($b, $a) -> $r }
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};
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}
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impl_vec_andc! { (vector_unsigned_char, ~vector_bool_char) -> vector_unsigned_char }
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impl_vec_andc! { (vector_signed_char, ~vector_bool_char) -> vector_signed_char }
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impl_vec_andc! { (vector_unsigned_short, ~vector_bool_short) -> vector_unsigned_short }
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impl_vec_andc! { (vector_signed_short, ~vector_bool_short) -> vector_signed_short }
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impl_vec_andc! { (vector_unsigned_int, ~vector_bool_int) -> vector_unsigned_int }
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impl_vec_andc! { (vector_signed_int, ~vector_bool_int) -> vector_signed_int }
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test_impl! { vec_vand(a: vector_signed_char, b: vector_signed_char) -> vector_signed_char [ simd_and, vand / xxland ] }
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pub trait VectorAnd<Other> {
@@ -1202,6 +1240,16 @@ mod sealed {
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vector_mladd! { vector_signed_short, vector_signed_short, vector_signed_short }
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}
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/// Vector andc.
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#[inline]
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#[target_feature(enable = "altivec")]
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pub unsafe fn vec_andc<T, U>(a: T, b: U) -> <T as sealed::VectorAndc<U>>::Result
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where
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T: sealed::VectorAndc<U>,
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{
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a.vec_andc(b)
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}
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/// Vector and.
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#[inline]
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#[target_feature(enable = "altivec")]
@@ -1516,6 +1564,11 @@ mod tests {
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}
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}
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test_vec_2! { test_vec_andc, vec_andc, i32x4,
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[0b11001100, 0b11001100, 0b11001100, 0b11001100],
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[0b00110011, 0b11110011, 0b00001100, 0b10000000],
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[0b11001100, 0b00001100, 0b11000000, 0b01001100] }
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test_vec_2! { test_vec_and, vec_and, i32x4,
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[0b11001100, 0b11001100, 0b11001100, 0b11001100],
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[0b00110011, 0b11110011, 0b00001100, 0b00000000],

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