@@ -18,18 +18,27 @@ pub unsafe fn _mm512_set_epi64(
18
18
e1 : i64 ,
19
19
e0 : i64 ,
20
20
) -> __m512i {
21
- let r = i64x8 ( e0, e1, e2, e3, e4, e5, e6, e7) ;
22
- transmute ( r)
21
+ _mm512_setr_epi64 ( e7, e6, e5, e4, e3, e2, e1, e0) ;
23
22
}
24
23
25
- /// Compare packed unsigned 64-bit integers in a and b for less-than, and store the results in a mask vector.
24
+ /// Sets packed 64-bit integers in `dst` with the supplied values in
25
+ /// reverse order.
26
26
///
27
- /// [Intel's documentation](https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062&text=_mm512_cmplt_epu64 )
27
+ /// [Intel's documentation]( https://software.intel.com/sites/landingpage/IntrinsicsGuide/#expand=727,1063,4909,1062,1062,4909 &text=_mm512_set_epi64 )
28
28
#[ inline]
29
29
#[ target_feature( enable = "avx512f" ) ]
30
- #[ cfg_attr( test, assert_instr( vpcmpuq) ) ]
31
- pub unsafe fn _mm512_cmplt_epu64_mask ( a : __m512i , b : __m512i ) -> __mmask8 {
32
- simd_bitmask :: < __m512i , _ > ( simd_lt ( a. as_u64x8 ( ) , b. as_u64x8 ( ) ) )
30
+ pub unsafe fn _mm512_setr_epi64 (
31
+ e7 : i64 ,
32
+ e6 : i64 ,
33
+ e5 : i64 ,
34
+ e4 : i64 ,
35
+ e3 : i64 ,
36
+ e2 : i64 ,
37
+ e1 : i64 ,
38
+ e0 : i64 ,
39
+ ) -> __m512i {
40
+ let r = i64x8 ( e0, e1, e2, e3, e4, e5, e6, e7) ;
41
+ transmute ( r)
33
42
}
34
43
35
44
#[ cfg( test) ]
@@ -47,4 +56,16 @@ mod tests {
47
56
let m = _mm512_cmplt_epu64_mask ( a, b) ;
48
57
assert_eq ! ( m, 0b11001111 ) ;
49
58
}
59
+
60
+ #[ simd_test( enable = "avx512f" ) ]
61
+ unsafe fn test_mm512_set_epi64 ( ) {
62
+ let r = _mm512_setr_epi64 ( 0 , 1 , 2 , 3 , 4 , 5 , 6 , 7 ) ;
63
+ assert_eq_m512i ( r, _mm512_set_epi64 ( 7 , 6 , 5 , 4 , 3 , 2 , 1 , 0 ) )
64
+ }
65
+
66
+ #[ simd_test( enable = "avx512f" ) ]
67
+ unsafe fn test_mm512_setr_epi64 ( ) {
68
+ let r = _mm512_set_epi64 ( 0 , 1 , 2 , 3 , 4 , 5 , 6 , 7 ) ;
69
+ assert_eq_m512i ( r, _mm512_setr_epi64 ( 7 , 6 , 5 , 4 , 3 , 2 , 1 , 0 ) )
70
+ }
50
71
}
0 commit comments