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fixup
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3 files changed

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3 files changed

+135
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‎coresimd/ppsv/api/arithmetic_reductions.rs

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,21 +5,62 @@ macro_rules! impl_arithmetic_reductions {
55
($id:ident, $elem_ty:ident) => {
66
impl $id {
77
/// Lane-wise addition of the vector elements.
8+
///
9+
/// FIXME: document guarantees with respect to:
10+
/// * integers: overflow behavior
11+
/// * floats: order and NaNs
12+
#[cfg(not(target_arch = "aarch64"))]
813
#[inline]
914
pub fn sum(self) -> $elem_ty {
1015
use ::coresimd::simd_llvm::simd_reduce_add_ordered;
1116
unsafe {
1217
simd_reduce_add_ordered(self, 0 as $elem_ty)
1318
}
1419
}
20+
/// Lane-wise addition of the vector elements.
21+
///
22+
/// FIXME: document guarantees with respect to:
23+
/// * integers: overflow behavior
24+
/// * floats: order and NaNs
25+
#[cfg(target_arch = "aarch64")]
26+
#[inline]
27+
pub fn sum(self) -> $elem_ty {
28+
// FIXME: broken on AArch64
29+
let mut x = self.extract(0) as $elem_ty;
30+
for i in 1..$id::lanes() {
31+
x += self.extract(i) as $elem_ty;
32+
}
33+
x
34+
}
35+
1536
/// Lane-wise multiplication of the vector elements.
37+
///
38+
/// FIXME: document guarantees with respect to:
39+
/// * integers: overflow behavior
40+
/// * floats: order and NaNs
41+
#[cfg(not(target_arch = "aarch64"))]
1642
#[inline]
1743
pub fn product(self) -> $elem_ty {
1844
use ::coresimd::simd_llvm::simd_reduce_mul_ordered;
1945
unsafe {
2046
simd_reduce_mul_ordered(self, 1 as $elem_ty)
2147
}
2248
}
49+
/// Lane-wise multiplication of the vector elements.
50+
///
51+
/// FIXME: document guarantees with respect to:
52+
/// * integers: overflow behavior
53+
/// * floats: order and NaNs
54+
#[cfg(target_arch = "aarch64")]
55+
#[inline]
56+
pub fn product(self) -> $elem_ty {
57+
// FIXME: broken on AArch64
58+
let mut x = self.extract(0) as $elem_ty;
59+
for i in 1..$id::lanes() {
60+
x *= self.extract(i) as $elem_ty;
61+
}
62+
x
63+
}
2364
}
2465
}
2566
}

‎coresimd/ppsv/api/bitwise_reductions.rs

Lines changed: 76 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,29 +5,67 @@ macro_rules! impl_bitwise_reductions {
55
($id:ident, $elem_ty:ident) => {
66
impl $id {
77
/// Lane-wise bitwise `and` of the vector elements.
8+
#[cfg(not(target_arch = "aarch64"))]
89
#[inline]
910
pub fn and(self) -> $elem_ty {
1011
use ::coresimd::simd_llvm::simd_reduce_and;
1112
unsafe {
1213
simd_reduce_and(self)
1314
}
1415
}
16+
/// Lane-wise bitwise `and` of the vector elements.
17+
#[cfg(target_arch = "aarch64")]
18+
#[inline]
19+
pub fn and(self) -> $elem_ty {
20+
// FIXME: broken on aarch64
21+
let mut x = self.extract(0) as $elem_ty;
22+
for i in 1..$id::lanes() {
23+
x &= self.extract(i) as $elem_ty;
24+
}
25+
x
26+
}
27+
1528
/// Lane-wise bitwise `or` of the vector elements.
29+
#[cfg(not(target_arch = "aarch64"))]
1630
#[inline]
1731
pub fn or(self) -> $elem_ty {
1832
use ::coresimd::simd_llvm::simd_reduce_or;
1933
unsafe {
2034
simd_reduce_or(self)
2135
}
2236
}
37+
/// Lane-wise bitwise `or` of the vector elements.
38+
#[cfg(target_arch = "aarch64")]
39+
#[inline]
40+
pub fn or(self) -> $elem_ty {
41+
// FIXME: broken on aarch64
42+
let mut x = self.extract(0) as $elem_ty;
43+
for i in 1..$id::lanes() {
44+
x |= self.extract(i) as $elem_ty;
45+
}
46+
x
47+
}
48+
2349
/// Lane-wise bitwise `xor` of the vector elements.
50+
#[cfg(not(target_arch = "aarch64"))]
2451
#[inline]
2552
pub fn xor(self) -> $elem_ty {
2653
use ::coresimd::simd_llvm::simd_reduce_xor;
2754
unsafe {
2855
simd_reduce_xor(self)
2956
}
3057
}
58+
/// Lane-wise bitwise `xor` of the vector elements.
59+
#[cfg(target_arch = "aarch64")]
60+
#[inline]
61+
pub fn xor(self) -> $elem_ty {
62+
// FIXME: broken on aarch64
63+
let mut x = self.extract(0) as $elem_ty;
64+
for i in 1..$id::lanes() {
65+
x ^= self.extract(i) as $elem_ty;
66+
}
67+
x
68+
}
3169
}
3270
}
3371
}
@@ -36,6 +74,7 @@ macro_rules! impl_bool_bitwise_reductions {
3674
($id:ident, $elem_ty:ident, $internal_ty:ident) => {
3775
impl $id {
3876
/// Lane-wise bitwise `and` of the vector elements.
77+
#[cfg(not(target_arch = "aarch64"))]
3978
#[inline]
4079
pub fn and(self) -> $elem_ty {
4180
use ::coresimd::simd_llvm::simd_reduce_and;
@@ -44,7 +83,20 @@ macro_rules! impl_bool_bitwise_reductions {
4483
r != 0
4584
}
4685
}
86+
/// Lane-wise bitwise `and` of the vector elements.
87+
#[cfg(target_arch = "aarch64")]
88+
#[inline]
89+
pub fn and(self) -> $elem_ty {
90+
// FIXME: broken on aarch64
91+
let mut x = self.extract(0) as $elem_ty;
92+
for i in 1..$id::lanes() {
93+
x &= self.extract(i) as $elem_ty;
94+
}
95+
x
96+
}
97+
4798
/// Lane-wise bitwise `or` of the vector elements.
99+
#[cfg(not(target_arch = "aarch64"))]
48100
#[inline]
49101
pub fn or(self) -> $elem_ty {
50102
use ::coresimd::simd_llvm::simd_reduce_or;
@@ -53,7 +105,20 @@ macro_rules! impl_bool_bitwise_reductions {
53105
r != 0
54106
}
55107
}
108+
/// Lane-wise bitwise `or` of the vector elements.
109+
#[cfg(target_arch = "aarch64")]
110+
#[inline]
111+
pub fn or(self) -> $elem_ty {
112+
// FIXME: broken on aarch64
113+
let mut x = self.extract(0) as $elem_ty;
114+
for i in 1..$id::lanes() {
115+
x |= self.extract(i) as $elem_ty;
116+
}
117+
x
118+
}
119+
56120
/// Lane-wise bitwise `xor` of the vector elements.
121+
#[cfg(not(target_arch = "aarch64"))]
57122
#[inline]
58123
pub fn xor(self) -> $elem_ty {
59124
use ::coresimd::simd_llvm::simd_reduce_xor;
@@ -62,6 +127,17 @@ macro_rules! impl_bool_bitwise_reductions {
62127
r != 0
63128
}
64129
}
130+
/// Lane-wise bitwise `xor` of the vector elements.
131+
#[cfg(target_arch = "aarch64")]
132+
#[inline]
133+
pub fn xor(self) -> $elem_ty {
134+
// FIXME: broken on aarch64
135+
let mut x = self.extract(0) as $elem_ty;
136+
for i in 1..$id::lanes() {
137+
x ^= self.extract(i) as $elem_ty;
138+
}
139+
x
140+
}
65141
}
66142
}
67143
}

‎coresimd/ppsv/api/boolean_reductions.rs

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,21 +5,39 @@ macro_rules! impl_bool_reductions {
55
($id:ident) => {
66
impl $id {
77
/// Are `all` vector lanes `true`?
8+
#[cfg(not(target_arch = "aarch64"))]
89
#[inline]
910
pub fn all(self) -> bool {
1011
use ::coresimd::simd_llvm::simd_reduce_all;
1112
unsafe {
1213
simd_reduce_all(self)
1314
}
1415
}
16+
/// Are `all` vector lanes `true`?
17+
#[cfg(target_arch = "aarch64")]
18+
#[inline]
19+
pub fn all(self) -> bool {
20+
// FIXME: Broken on AArch64
21+
self.and()
22+
}
23+
1524
/// Is `any` vector lanes `true`?
25+
#[cfg(not(target_arch = "aarch64"))]
1626
#[inline]
1727
pub fn any(self) -> bool {
1828
use ::coresimd::simd_llvm::simd_reduce_any;
1929
unsafe {
2030
simd_reduce_any(self)
2131
}
2232
}
33+
/// Is `any` vector lanes `true`?
34+
#[cfg(target_arch = "aarch64")]
35+
#[inline]
36+
pub fn any(self) -> bool {
37+
// FIXME: Broken on AArch64
38+
self.or()
39+
}
40+
2341
/// Are `all` vector lanes `false`?
2442
#[inline]
2543
pub fn none(self) -> bool {

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