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Add vdiv neon instructions #1077

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68 changes: 68 additions & 0 deletions crates/core_arch/src/aarch64/neon/generated.rs
Original file line number Diff line number Diff line change
Expand Up @@ -1031,6 +1031,38 @@ pub unsafe fn vmulq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
simd_mul(a, b)
}

/// Divide
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fdiv))]
pub unsafe fn vdiv_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
simd_div(a, b)
}

/// Divide
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fdiv))]
pub unsafe fn vdivq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
simd_div(a, b)
}

/// Divide
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fdiv))]
pub unsafe fn vdiv_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
simd_div(a, b)
}

/// Divide
#[inline]
#[target_feature(enable = "neon")]
#[cfg_attr(test, assert_instr(fdiv))]
pub unsafe fn vdivq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
simd_div(a, b)
}

/// Subtract
#[inline]
#[target_feature(enable = "neon")]
Expand Down Expand Up @@ -2112,6 +2144,42 @@ mod test {
assert_eq!(r, e);
}

#[simd_test(enable = "neon")]
unsafe fn test_vdiv_f32() {
let a: f32x2 = f32x2::new(2.0, 6.0);
let b: f32x2 = f32x2::new(1.0, 2.0);
let e: f32x2 = f32x2::new(2.0, 3.0);
let r: f32x2 = transmute(vdiv_f32(transmute(a), transmute(b)));
assert_eq!(r, e);
}

#[simd_test(enable = "neon")]
unsafe fn test_vdivq_f32() {
let a: f32x4 = f32x4::new(2.0, 6.0, 4.0, 10.0);
let b: f32x4 = f32x4::new(1.0, 2.0, 1.0, 2.0);
let e: f32x4 = f32x4::new(2.0, 3.0, 4.0, 5.0);
let r: f32x4 = transmute(vdivq_f32(transmute(a), transmute(b)));
assert_eq!(r, e);
}

#[simd_test(enable = "neon")]
unsafe fn test_vdiv_f64() {
let a: f64 = 2.0;
let b: f64 = 1.0;
let e: f64 = 2.0;
let r: f64 = transmute(vdiv_f64(transmute(a), transmute(b)));
assert_eq!(r, e);
}

#[simd_test(enable = "neon")]
unsafe fn test_vdivq_f64() {
let a: f64x2 = f64x2::new(2.0, 6.0);
let b: f64x2 = f64x2::new(1.0, 2.0);
let e: f64x2 = f64x2::new(2.0, 3.0);
let r: f64x2 = transmute(vdivq_f64(transmute(a), transmute(b)));
assert_eq!(r, e);
}

#[simd_test(enable = "neon")]
unsafe fn test_vsub_f64() {
let a: f64 = 1.0;
Expand Down
9 changes: 9 additions & 0 deletions crates/stdarch-gen/neon.spec
Original file line number Diff line number Diff line change
Expand Up @@ -601,6 +601,15 @@ generate float64x*_t
arm = vmul.
generate float*_t

/// Divide
name = vdiv
fn = simd_div
a = 2.0, 6.0, 4.0, 10.0
b = 1.0, 2.0, 1.0, 2.0
validate 2.0, 3.0, 4.0, 5.0

aarch64 = fdiv
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Can you generate arm versions of this which use the vdiv instruction?

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Note that arm only supports f32 variants: f64 is aarch64-only.

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According to the docs the supported architectures are only A64: https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics?search=vdiv

Supported architectures
A64

Maybe the docs are wrong?

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Ah you are correct, it seems the ARM vdiv instruction only supports scalar division, not vector division.

generate float*_t, float64x*_t

/// Subtract
name = vsub
Expand Down