Add shift-and-insert Arm intrinsics. #936
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| "vsli_n_s8", | ||
| "vsliq_n_s8", | ||
| "vsli_n_s16", | ||
| "vsliq_n_s16", | ||
| "vsli_n_s32", | ||
| "vsliq_n_s32", | ||
| "vsli_n_s64", |
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I seem to have to add these for the verify_all_signatures tests to pass, I'm guessing because I've put the shift-and-insert tests in their own file (mimicking what's done for the table lookup tests, which also appear in this list of signatures to skip).
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I believe that they are not being detected because you are generating the tests within a macro.
| #[rustc_args_required_const(2)] | ||
| pub unsafe fn vsli_n_s8(a: int8x8_t, b: int8x8_t, n: i32) -> int8x8_t { | ||
| if n < 0 || n > 7 { | ||
| unreachable_unchecked(); |
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Use a panic here for out-of-bounds values. It's optimized away in practice since this function is going to be inlined.
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Sounds good, will do 👍
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☔ The latest upstream changes (presumably dd981c0) made this pull request unmergeable. Please resolve the merge conflicts. Note that reviewers usually do not review pull requests until merge conflicts are resolved! Once you resolve the conflicts, you should change the labels applied by bors to indicate that your PR is ready for review. Post this as a comment to change the labels: |
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@rustbot modify labels: +S-waiting-on-review -S-waiting-on-author |
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Error: The feature Please let |
This PR adds Arm and Aarch64 Neon intrinsics for shift-left-and-insert and shift-right-and-insert.
The LLVM codegen for these instructions is quite different on Arm vs Aarch64. In the former case, both
vsliandvsriget transformed tollvm.arm.neon.vshiftins, which takes three equal-length vector arguments, where the last argument contains the per-element shift (which can be negative, for a right shift). In the latter case,vsliandvsriare transformed tollvm.aarch64.neon.vsliandllvm.aarch64.neon.vsrirespectively, which takes two vector inputs and a constant for the shift.