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jurahuljurahul
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[NFC] Cleanup RegisterInfoEmitter code (llvm#109199)
Change variable name `o` to `OS` to match definition, and `ClName` to `ClassName` for better clarity. Cache RegBank reference in the class and do no pass around class members to functions.
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‎llvm/utils/TableGen/RegisterInfoEmitter.cpp

Lines changed: 38 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -56,54 +56,49 @@ static cl::opt<bool>
5656
namespace {
5757

5858
class RegisterInfoEmitter {
59-
CodeGenTarget Target;
6059
RecordKeeper &Records;
60+
const CodeGenTarget Target;
61+
CodeGenRegBank &RegBank;
6162

6263
public:
63-
RegisterInfoEmitter(RecordKeeper &R) : Target(R), Records(R) {
64-
CodeGenRegBank &RegBank = Target.getRegBank();
64+
RegisterInfoEmitter(RecordKeeper &R)
65+
: Records(R), Target(R), RegBank(Target.getRegBank()) {
6566
RegBank.computeDerivedInfo();
6667
}
6768

6869
// runEnums - Print out enum values for all of the registers.
69-
void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
70+
void runEnums(raw_ostream &OS);
7071

7172
// runMCDesc - Print out MC register descriptions.
72-
void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
73+
void runMCDesc(raw_ostream &OS);
7374

7475
// runTargetHeader - Emit a header fragment for the register info emitter.
75-
void runTargetHeader(raw_ostream &o, CodeGenTarget &Target,
76-
CodeGenRegBank &Bank);
76+
void runTargetHeader(raw_ostream &OS);
7777

7878
// runTargetDesc - Output the target register and register file descriptions.
79-
void runTargetDesc(raw_ostream &o, CodeGenTarget &Target,
80-
CodeGenRegBank &Bank);
79+
void runTargetDesc(raw_ostream &OS);
8180

8281
// run - Output the register file description.
83-
void run(raw_ostream &o);
82+
void run(raw_ostream &OS);
8483

8584
void debugDump(raw_ostream &OS);
8685

8786
private:
88-
void EmitRegMapping(raw_ostream &o, const std::deque<CodeGenRegister> &Regs,
87+
void EmitRegMapping(raw_ostream &OS, const std::deque<CodeGenRegister> &Regs,
8988
bool isCtor);
90-
void EmitRegMappingTables(raw_ostream &o,
89+
void EmitRegMappingTables(raw_ostream &OS,
9190
const std::deque<CodeGenRegister> &Regs,
9291
bool isCtor);
93-
void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
94-
const std::string &ClassName);
95-
void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
96-
const std::string &ClassName);
97-
void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
98-
const std::string &ClassName);
92+
void EmitRegUnitPressure(raw_ostream &OS, StringRef ClassName);
93+
void emitComposeSubRegIndices(raw_ostream &OS, StringRef ClassName);
94+
void emitComposeSubRegIndexLaneMask(raw_ostream &OS, StringRef ClassName);
9995
};
10096

10197
} // end anonymous namespace
10298

10399
// runEnums - Print out enum values for all of the registers.
104-
void RegisterInfoEmitter::runEnums(raw_ostream &OS, CodeGenTarget &Target,
105-
CodeGenRegBank &Bank) {
106-
const auto &Registers = Bank.getRegisters();
100+
void RegisterInfoEmitter::runEnums(raw_ostream &OS) {
101+
const auto &Registers = RegBank.getRegisters();
107102

108103
// Register enums are stored as uint16_t in the tables. Make sure we'll fit.
109104
assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
@@ -134,7 +129,7 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS, CodeGenTarget &Target,
134129
if (!Namespace.empty())
135130
OS << "} // end namespace " << Namespace << "\n";
136131

137-
const auto &RegisterClasses = Bank.getRegClasses();
132+
const auto &RegisterClasses = RegBank.getRegClasses();
138133
if (!RegisterClasses.empty()) {
139134

140135
// RegisterClass enums are stored as uint16_t in the tables.
@@ -168,7 +163,7 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS, CodeGenTarget &Target,
168163
OS << "} // end namespace " << Namespace << "\n\n";
169164
}
170165

171-
auto &SubRegIndices = Bank.getSubRegIndices();
166+
auto &SubRegIndices = RegBank.getSubRegIndices();
172167
if (!SubRegIndices.empty()) {
173168
OS << "\n// Subregister indices\n\n";
174169
std::string Namespace = SubRegIndices.front().getNamespace();
@@ -187,9 +182,9 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS, CodeGenTarget &Target,
187182
if (!Namespace.empty())
188183
OS << "namespace " << Namespace << " {\n";
189184
OS << "enum RegisterPressureSets {\n";
190-
unsigned NumSets = Bank.getNumRegPressureSets();
185+
unsigned NumSets = RegBank.getNumRegPressureSets();
191186
for (unsigned i = 0; i < NumSets; ++i) {
192-
const RegUnitSet &RegUnits = Bank.getRegSetAt(i);
187+
const RegUnitSet &RegUnits = RegBank.getRegSetAt(i);
193188
OS << " " << RegUnits.Name << " = " << i << ",\n";
194189
}
195190
OS << "};\n";
@@ -204,8 +199,7 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS, CodeGenTarget &Target,
204199
static void printInt(raw_ostream &OS, int Val) { OS << Val; }
205200

206201
void RegisterInfoEmitter::EmitRegUnitPressure(raw_ostream &OS,
207-
const CodeGenRegBank &RegBank,
208-
const std::string &ClassName) {
202+
StringRef ClassName) {
209203
unsigned NumRCs = RegBank.getRegClasses().size();
210204
unsigned NumSets = RegBank.getNumRegPressureSets();
211205

@@ -683,10 +677,9 @@ static bool combine(const CodeGenSubRegIndex *Idx,
683677
}
684678

685679
void RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS,
686-
CodeGenRegBank &RegBank,
687-
const std::string &ClName) {
680+
StringRef ClassName) {
688681
const auto &SubRegIndices = RegBank.getSubRegIndices();
689-
OS << "unsigned " << ClName
682+
OS << "unsigned " << ClassName
690683
<< "::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {\n";
691684

692685
// Many sub-register indexes are composition-compatible, meaning that
@@ -751,8 +744,8 @@ void RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS,
751744
OS << "}\n\n";
752745
}
753746

754-
void RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(
755-
raw_ostream &OS, CodeGenRegBank &RegBank, const std::string &ClName) {
747+
void RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS,
748+
StringRef ClassName) {
756749
// See the comments in computeSubRegLaneMasks() for our goal here.
757750
const auto &SubRegIndices = RegBank.getSubRegIndices();
758751

@@ -815,7 +808,7 @@ void RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(
815808
}
816809
OS << " };\n\n";
817810

818-
OS << "LaneBitmask " << ClName
811+
OS << "LaneBitmask " << ClassName
819812
<< "::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask)"
820813
" const {\n"
821814
" --IdxA; assert(IdxA < "
@@ -836,7 +829,7 @@ void RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(
836829
" return Result;\n"
837830
"}\n\n";
838831

839-
OS << "LaneBitmask " << ClName
832+
OS << "LaneBitmask " << ClassName
840833
<< "::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, "
841834
" LaneBitmask LaneMask) const {\n"
842835
" LaneMask &= getSubRegIndexLaneMask(IdxA);\n"
@@ -861,8 +854,7 @@ void RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(
861854
//
862855
// runMCDesc - Print out MC register descriptions.
863856
//
864-
void RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
865-
CodeGenRegBank &RegBank) {
857+
void RegisterInfoEmitter::runMCDesc(raw_ostream &OS) {
866858
emitSourceFileHeader("MC Register Information", OS);
867859

868860
OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
@@ -1025,7 +1017,7 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
10251017
<< " const uint8_t " << Name << "Bits[] = {\n ";
10261018
BitVectorEmitter BVE;
10271019
for (const Record *Reg : Order) {
1028-
BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
1020+
BVE.add(RegBank.getReg(Reg)->EnumValue);
10291021
}
10301022
BVE.print(OS);
10311023
OS << "\n };\n\n";
@@ -1100,9 +1092,7 @@ void RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
11001092
OS << "#endif // GET_REGINFO_MC_DESC\n\n";
11011093
}
11021094

1103-
void RegisterInfoEmitter::runTargetHeader(raw_ostream &OS,
1104-
CodeGenTarget &Target,
1105-
CodeGenRegBank &RegBank) {
1095+
void RegisterInfoEmitter::runTargetHeader(raw_ostream &OS) {
11061096
emitSourceFileHeader("Register Information Header Fragment", OS);
11071097

11081098
OS << "\n#ifdef GET_REGINFO_HEADER\n";
@@ -1187,8 +1177,7 @@ void RegisterInfoEmitter::runTargetHeader(raw_ostream &OS,
11871177
//
11881178
// runTargetDesc - Output the target register and register file descriptions.
11891179
//
1190-
void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
1191-
CodeGenRegBank &RegBank) {
1180+
void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS) {
11921181
emitSourceFileHeader("Target Register and Register Classes Information", OS);
11931182

11941183
OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
@@ -1491,8 +1480,8 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
14911480
std::distance(SubRegIndices.begin(), SubRegIndices.end());
14921481

14931482
if (!SubRegIndices.empty()) {
1494-
emitComposeSubRegIndices(OS, RegBank, ClassName);
1495-
emitComposeSubRegIndexLaneMask(OS, RegBank, ClassName);
1483+
emitComposeSubRegIndices(OS, ClassName);
1484+
emitComposeSubRegIndexLaneMask(OS, ClassName);
14961485
}
14971486

14981487
if (!SubRegIndices.empty()) {
@@ -1574,7 +1563,7 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
15741563
<< " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n";
15751564
}
15761565

1577-
EmitRegUnitPressure(OS, RegBank, ClassName);
1566+
EmitRegUnitPressure(OS, ClassName);
15781567

15791568
// Emit register base class mapper
15801569
if (!RegisterClasses.empty()) {
@@ -1816,25 +1805,23 @@ void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
18161805
}
18171806

18181807
void RegisterInfoEmitter::run(raw_ostream &OS) {
1819-
CodeGenRegBank &RegBank = Target.getRegBank();
18201808
Records.startTimer("Print enums");
1821-
runEnums(OS, Target, RegBank);
1809+
runEnums(OS);
18221810

18231811
Records.startTimer("Print MC registers");
1824-
runMCDesc(OS, Target, RegBank);
1812+
runMCDesc(OS);
18251813

18261814
Records.startTimer("Print header fragment");
1827-
runTargetHeader(OS, Target, RegBank);
1815+
runTargetHeader(OS);
18281816

18291817
Records.startTimer("Print target registers");
1830-
runTargetDesc(OS, Target, RegBank);
1818+
runTargetDesc(OS);
18311819

18321820
if (RegisterInfoDebug)
18331821
debugDump(errs());
18341822
}
18351823

18361824
void RegisterInfoEmitter::debugDump(raw_ostream &OS) {
1837-
CodeGenRegBank &RegBank = Target.getRegBank();
18381825
const CodeGenHwModes &CGH = Target.getHwModes();
18391826
unsigned NumModes = CGH.getNumModeIds();
18401827
auto getModeName = [CGH](unsigned M) -> StringRef {

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