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[GlobalISel] LegalizerHelper - Extract widenScalarAddoSubo method
The widenScalar implementation for signed and unsigned overflowing operations were very similar: both are checked by truncating the result and then re-sign/zero-extending it and checking that it matches the computed operation. Using a truncate + zero-extend for the unsigned case instead of manually producing the AND instruction like before leads to an extra copy instruction during legalization, but this should be harmless. Differential Revision: https://reviews.llvm.org/D95035
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8 files changed

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‎llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -170,8 +170,10 @@ class LegalizerHelper {
170170
widenScalarExtract(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
171171
LegalizeResult
172172
widenScalarInsert(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
173-
LegalizeResult
174-
widenScalarAddSubShlSat(MachineInstr &MI, unsigned TypeIdx, LLT WideTy);
173+
LegalizeResult widenScalarAddoSubo(MachineInstr &MI, unsigned TypeIdx,
174+
LLT WideTy);
175+
LegalizeResult widenScalarAddSubShlSat(MachineInstr &MI, unsigned TypeIdx,
176+
LLT WideTy);
175177

176178
/// Helper function to split a wide generic register into bitwise blocks with
177179
/// the given Type (which implies the number of blocks needed). The generic

‎llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

Lines changed: 31 additions & 41 deletions
Original file line numberDiff line numberDiff line change
@@ -1757,6 +1757,34 @@ LegalizerHelper::widenScalarInsert(MachineInstr &MI, unsigned TypeIdx,
17571757
return Legalized;
17581758
}
17591759

1760+
LegalizerHelper::LegalizeResult
1761+
LegalizerHelper::widenScalarAddoSubo(MachineInstr &MI, unsigned TypeIdx,
1762+
LLT WideTy) {
1763+
if (TypeIdx == 1)
1764+
return UnableToLegalize; // TODO
1765+
unsigned Op = MI.getOpcode();
1766+
unsigned Opcode = Op == TargetOpcode::G_UADDO || Op == TargetOpcode::G_SADDO
1767+
? TargetOpcode::G_ADD
1768+
: TargetOpcode::G_SUB;
1769+
unsigned ExtOpcode =
1770+
Op == TargetOpcode::G_UADDO || Op == TargetOpcode::G_USUBO
1771+
? TargetOpcode::G_ZEXT
1772+
: TargetOpcode::G_SEXT;
1773+
auto LHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(2)});
1774+
auto RHSExt = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MI.getOperand(3)});
1775+
// Do the arithmetic in the larger type.
1776+
auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSExt, RHSExt});
1777+
LLT OrigTy = MRI.getType(MI.getOperand(0).getReg());
1778+
auto TruncOp = MIRBuilder.buildTrunc(OrigTy, NewOp);
1779+
auto ExtOp = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {TruncOp});
1780+
// There is no overflow if the ExtOp is the same as NewOp.
1781+
MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1), NewOp, ExtOp);
1782+
// Now trunc the NewOp to the original result.
1783+
MIRBuilder.buildTrunc(MI.getOperand(0), NewOp);
1784+
MI.eraseFromParent();
1785+
return Legalized;
1786+
}
1787+
17601788
LegalizerHelper::LegalizeResult
17611789
LegalizerHelper::widenScalarAddSubShlSat(MachineInstr &MI, unsigned TypeIdx,
17621790
LLT WideTy) {
@@ -1815,48 +1843,10 @@ LegalizerHelper::widenScalar(MachineInstr &MI, unsigned TypeIdx, LLT WideTy) {
18151843
case TargetOpcode::G_UNMERGE_VALUES:
18161844
return widenScalarUnmergeValues(MI, TypeIdx, WideTy);
18171845
case TargetOpcode::G_SADDO:
1818-
case TargetOpcode::G_SSUBO: {
1819-
if (TypeIdx == 1)
1820-
return UnableToLegalize; // TODO
1821-
auto LHSExt = MIRBuilder.buildSExt(WideTy, MI.getOperand(2));
1822-
auto RHSExt = MIRBuilder.buildSExt(WideTy, MI.getOperand(3));
1823-
unsigned Opcode = MI.getOpcode() == TargetOpcode::G_SADDO
1824-
? TargetOpcode::G_ADD
1825-
: TargetOpcode::G_SUB;
1826-
auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSExt, RHSExt});
1827-
LLT OrigTy = MRI.getType(MI.getOperand(0).getReg());
1828-
auto TruncOp = MIRBuilder.buildTrunc(OrigTy, NewOp);
1829-
auto ExtOp = MIRBuilder.buildSExt(WideTy, TruncOp);
1830-
// There is no overflow if the re-extended result is the same as NewOp.
1831-
MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1), NewOp, ExtOp);
1832-
// Now trunc the NewOp to the original result.
1833-
MIRBuilder.buildTrunc(MI.getOperand(0), NewOp);
1834-
MI.eraseFromParent();
1835-
return Legalized;
1836-
}
1846+
case TargetOpcode::G_SSUBO:
18371847
case TargetOpcode::G_UADDO:
1838-
case TargetOpcode::G_USUBO: {
1839-
if (TypeIdx == 1)
1840-
return UnableToLegalize; // TODO
1841-
auto LHSZext = MIRBuilder.buildZExt(WideTy, MI.getOperand(2));
1842-
auto RHSZext = MIRBuilder.buildZExt(WideTy, MI.getOperand(3));
1843-
unsigned Opcode = MI.getOpcode() == TargetOpcode::G_UADDO
1844-
? TargetOpcode::G_ADD
1845-
: TargetOpcode::G_SUB;
1846-
// Do the arithmetic in the larger type.
1847-
auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSZext, RHSZext});
1848-
LLT OrigTy = MRI.getType(MI.getOperand(0).getReg());
1849-
APInt Mask =
1850-
APInt::getLowBitsSet(WideTy.getSizeInBits(), OrigTy.getSizeInBits());
1851-
auto AndOp = MIRBuilder.buildAnd(
1852-
WideTy, NewOp, MIRBuilder.buildConstant(WideTy, Mask));
1853-
// There is no overflow if the AndOp is the same as NewOp.
1854-
MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1), NewOp, AndOp);
1855-
// Now trunc the NewOp to the original result.
1856-
MIRBuilder.buildTrunc(MI.getOperand(0), NewOp);
1857-
MI.eraseFromParent();
1858-
return Legalized;
1859-
}
1848+
case TargetOpcode::G_USUBO:
1849+
return widenScalarAddoSubo(MI, TypeIdx, WideTy);
18601850
case TargetOpcode::G_SADDSAT:
18611851
case TargetOpcode::G_SSUBSAT:
18621852
case TargetOpcode::G_SSHLSAT:

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -87,7 +87,8 @@ body: |
8787
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
8888
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
8989
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
90-
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
90+
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
91+
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
9192
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
9293
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32)
9394
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-sub.mir

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -107,7 +107,8 @@ body: |
107107
; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
108108
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[TRUNC1]], [[C]]
109109
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
110-
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
110+
; CHECK: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
111+
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
111112
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
112113
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32)
113114
; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)

‎llvm/test/CodeGen/AArch64/legalize-uaddo.mir

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,8 +18,11 @@ body: |
1818
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[C]]
1919
; CHECK: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
2020
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[C1]]
21-
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
21+
; CHECK: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ADD]](s32)
22+
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
23+
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
2224
; CHECK: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ne), [[ADD]](s32), [[AND1]]
25+
; CHECK: [[COPY2:%[0-9]+]]:_(s16) = COPY [[TRUNC1]](s16)
2326
; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
2427
; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ICMP]](s32)
2528
; CHECK: [[AND2:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C2]]

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -37,10 +37,11 @@ body: |
3737
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
3838
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
3939
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
40-
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
41-
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
4240
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
43-
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
41+
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
42+
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
43+
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
44+
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
4445
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
4546
; CHECK: $vgpr0 = COPY [[AND3]](s32)
4647
; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
@@ -71,10 +72,11 @@ body: |
7172
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
7273
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
7374
; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AND]], [[AND1]]
74-
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[ADD]], [[C]]
75-
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
7675
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
77-
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
76+
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
77+
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD]](s32), [[AND2]]
78+
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD]](s32)
79+
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
7880
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
7981
; CHECK: $vgpr0 = COPY [[AND3]](s32)
8082
; CHECK: $vgpr1 = COPY [[ZEXT]](s32)

‎llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -37,10 +37,11 @@ body: |
3737
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
3838
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
3939
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
40-
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
41-
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
4240
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
43-
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
41+
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
42+
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
43+
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
44+
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
4445
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
4546
; CHECK: $vgpr0 = COPY [[AND3]](s32)
4647
; CHECK: $vgpr1 = COPY [[ZEXT]](s32)
@@ -71,10 +72,11 @@ body: |
7172
; CHECK: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
7273
; CHECK: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY3]], [[C]]
7374
; CHECK: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[AND]], [[AND1]]
74-
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[SUB]], [[C]]
75-
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
7675
; CHECK: [[COPY4:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
77-
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
76+
; CHECK: [[AND2:%[0-9]+]]:_(s32) = G_AND [[COPY4]], [[C]]
77+
; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[SUB]](s32), [[AND2]]
78+
; CHECK: [[COPY5:%[0-9]+]]:_(s32) = COPY [[SUB]](s32)
79+
; CHECK: [[AND3:%[0-9]+]]:_(s32) = G_AND [[COPY5]], [[C]]
7880
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
7981
; CHECK: $vgpr0 = COPY [[AND3]](s32)
8082
; CHECK: $vgpr1 = COPY [[ZEXT]](s32)

‎llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp

Lines changed: 84 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -589,9 +589,9 @@ TEST_F(AArch64GISelMITest, WidenUADDO) {
589589
CHECK: [[LHS:%[0-9]+]]:_(s16) = G_ZEXT [[Trunc]]
590590
CHECK: [[RHS:%[0-9]+]]:_(s16) = G_ZEXT [[Trunc]]
591591
CHECK: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[LHS]]:_, [[RHS]]:_
592-
CHECK: [[CST:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
593-
CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[ADD]]:_, [[CST]]:_
594-
CHECK: G_ICMP intpred(ne), [[ADD]]:_(s16), [[AND]]:_
592+
CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[ADD]]
593+
CHECK: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[TRUNC1]]
594+
CHECK: G_ICMP intpred(ne), [[ADD]]:_(s16), [[ZEXT]]:_
595595
CHECK: G_TRUNC [[ADD]]
596596
)";
597597

@@ -628,9 +628,87 @@ TEST_F(AArch64GISelMITest, WidenUSUBO) {
628628
CHECK: [[LHS:%[0-9]+]]:_(s16) = G_ZEXT [[Trunc]]
629629
CHECK: [[RHS:%[0-9]+]]:_(s16) = G_ZEXT [[Trunc]]
630630
CHECK: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[LHS]]:_, [[RHS]]:_
631-
CHECK: [[CST:%[0-9]+]]:_(s16) = G_CONSTANT i16 255
632-
CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[SUB]]:_, [[CST]]:_
633-
CHECK: G_ICMP intpred(ne), [[SUB]]:_(s16), [[AND]]:_
631+
CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[SUB]]
632+
CHECK: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[TRUNC1]]
633+
CHECK: G_ICMP intpred(ne), [[SUB]]:_(s16), [[ZEXT]]:_
634+
CHECK: G_TRUNC [[SUB]]
635+
)";
636+
637+
// Check
638+
EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
639+
}
640+
641+
// SADDO widening.
642+
TEST_F(AArch64GISelMITest, WidenSADDO) {
643+
setUp();
644+
if (!TM)
645+
return;
646+
647+
// Declare your legalization info
648+
DefineLegalizerInfo(A, {
649+
getActionDefinitionsBuilder(G_ADD).legalFor({{s16, s16}});
650+
});
651+
// Build
652+
// Trunc it to s8.
653+
LLT s8{LLT::scalar(8)};
654+
LLT s16{LLT::scalar(16)};
655+
auto MIBTrunc = B.buildTrunc(s8, Copies[0]);
656+
unsigned CarryReg = MRI->createGenericVirtualRegister(LLT::scalar(1));
657+
auto MIBSAddO =
658+
B.buildInstr(TargetOpcode::G_SADDO, {s8, CarryReg}, {MIBTrunc, MIBTrunc});
659+
AInfo Info(MF->getSubtarget());
660+
DummyGISelObserver Observer;
661+
LegalizerHelper Helper(*MF, Info, Observer, B);
662+
EXPECT_TRUE(Helper.widenScalar(*MIBSAddO, 0, s16) ==
663+
LegalizerHelper::LegalizeResult::Legalized);
664+
665+
auto CheckStr = R"(
666+
CHECK: [[Trunc:%[0-9]+]]:_(s8) = G_TRUNC
667+
CHECK: [[LHS:%[0-9]+]]:_(s16) = G_SEXT [[Trunc]]
668+
CHECK: [[RHS:%[0-9]+]]:_(s16) = G_SEXT [[Trunc]]
669+
CHECK: [[ADD:%[0-9]+]]:_(s16) = G_ADD [[LHS]]:_, [[RHS]]:_
670+
CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[ADD]]
671+
CHECK: [[SEXT:%[0-9]+]]:_(s16) = G_SEXT [[TRUNC1]]
672+
CHECK: G_ICMP intpred(ne), [[ADD]]:_(s16), [[SEXT]]:_
673+
CHECK: G_TRUNC [[ADD]]
674+
)";
675+
676+
// Check
677+
EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
678+
}
679+
680+
// SSUBO widening.
681+
TEST_F(AArch64GISelMITest, WidenSSUBO) {
682+
setUp();
683+
if (!TM)
684+
return;
685+
686+
// Declare your legalization info
687+
DefineLegalizerInfo(A, {
688+
getActionDefinitionsBuilder(G_SUB).legalFor({{s16, s16}});
689+
});
690+
// Build
691+
// Trunc it to s8.
692+
LLT s8{LLT::scalar(8)};
693+
LLT s16{LLT::scalar(16)};
694+
auto MIBTrunc = B.buildTrunc(s8, Copies[0]);
695+
unsigned CarryReg = MRI->createGenericVirtualRegister(LLT::scalar(1));
696+
auto MIBSSUBO =
697+
B.buildInstr(TargetOpcode::G_SSUBO, {s8, CarryReg}, {MIBTrunc, MIBTrunc});
698+
AInfo Info(MF->getSubtarget());
699+
DummyGISelObserver Observer;
700+
LegalizerHelper Helper(*MF, Info, Observer, B);
701+
EXPECT_TRUE(Helper.widenScalar(*MIBSSUBO, 0, s16) ==
702+
LegalizerHelper::LegalizeResult::Legalized);
703+
704+
auto CheckStr = R"(
705+
CHECK: [[Trunc:%[0-9]+]]:_(s8) = G_TRUNC
706+
CHECK: [[LHS:%[0-9]+]]:_(s16) = G_SEXT [[Trunc]]
707+
CHECK: [[RHS:%[0-9]+]]:_(s16) = G_SEXT [[Trunc]]
708+
CHECK: [[SUB:%[0-9]+]]:_(s16) = G_SUB [[LHS]]:_, [[RHS]]:_
709+
CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[SUB]]
710+
CHECK: [[SEXT:%[0-9]+]]:_(s16) = G_SEXT [[TRUNC1]]
711+
CHECK: G_ICMP intpred(ne), [[SUB]]:_(s16), [[SEXT]]:_
634712
CHECK: G_TRUNC [[SUB]]
635713
)";
636714

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